Patents Examined by Daniel McMahon
  • Error detection and correction in ternary content addressable memory (TCAM)
    Patent number: 9762261
    Abstract: A ternary content addressable memory (TCAM) is disclosed. The TCAM includes a memory array, a data match module, and compare circuitry. The memory array stores a data entry for a data word and a corresponding duplicate data entry for the data word. The data match module compares the data entry to an input word to produce a first match output, and compares the duplicate data entry to the input word to produce a second match output. The compare circuitry compares the first match output and the second match output.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 12, 2017
    Assignee: eSilicon Corporation
    Inventors: Michael Anthony Zampaglione, Thomas Robert Wik
  • Fast log-likelihood ratio (LLR) computation for decoding high-order and high-dimensional modulation schemes
    Patent number: 9749089
    Abstract: A method receives the symbol transmitted over a channel, selects, from a constellation of codewords, a first codeword neighboring the received symbol and a set of second codewords neighboring the first codeword, and determines a relative likelihood of each second codeword being the transmitted symbol with respect to a likelihood of the first codeword being the transmitted symbol. Next, the method determines an approximation of a log-likelihood ratio (LLR) of each data bit in the received symbol as a log of a ratio of a sum of the relative likelihoods of at least some of the second codewords having the same value of the data bit to a sum of the relative likelihoods of at least some of the second codewords having different value of the data bit and decodes the received symbol using the LLR of each data bit.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: August 29, 2017
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: David Millar, Toshiaki Koike-Akino, Keisuke Kojima, Kieran Parsons
  • Data encoding in solid-state storage apparatus
    Patent number: 9734010
    Abstract: A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of qary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of qary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of qary symbols via a second drift-tolerant encoding scheme; and supplying the qary symbols of the first and second groups for storage in respective q-level memory cells.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Secure communication method and system based on bit error probability
    Patent number: 9735925
    Abstract: Provided is a method for performing Hybrid Automatic Repeat Request (HARQ) by a data transmitting terminal in a wireless communication system. The terminal transmits data using a specific code word selected from a plurality of code words included in a mother code, calculates a Bit Error Rate (BER) upper bound for a receiving terminal that receives the data, calculates a BER lower bound for another terminal that is able to eavesdrop the data, and performs the HARQ based on whether the BER upper bound is greater than a BER reference level for the receiving terminal and whether a probability of the BER lower bound being less than the BER reference level for the another terminal is less than a predetermined value.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 15, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Joonkui Ahn, Ilmin Kim, Byounghoon Kim
  • Optimized chain diagnostic fail isolation
    Patent number: 9733307
    Abstract: A method, system, and/or computer program product of scanning of an integrated circuit including chiplets to isolate fault locations is provided herein. The scanning of the integrated circuit includes providing, by a pervasive of the integrated circuit, an input to the chiplets. Each of the chiplets can include a pervasive satellite, a multiplexer, and latches. The scanning of the integrated circuit includes also scanning, by each pervasive satellite of the chiplets, data based on the input via the multiplexer into the latches to produce scan data for each of the chiplets. The scanning of the integrated circuit also includes comparing, by the pervasive of the integrated circuit, the scan data of each of the chiplets to expectant data stored on the pervasive to isolate the fault locations.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard M. Salem, Andrew A. Turner
  • Packet transmission and reception system, apparatus, and method
    Patent number: 9729279
    Abstract: Provided are a packet transmission and reception system, apparatus, and method. The packet transmission and reception system for distributing and transmitting data through a plurality of multi-lanes includes a first transmission and reception apparatus configured to include a plurality of first physical lanes and a plurality of first logical lanes connected to the plurality of first physical lanes, and a second transmission and reception apparatus configured to include a plurality of second physical lanes and a plurality of second logical lanes connected to the plurality of second physical lanes.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 8, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Seok Choi, Hyuk Je Kwon
  • Non-binary low density parity check code column rotation
    Patent number: 9727419
    Abstract: An apparatus for processing data includes a storage medium operable to store encoded data, and a read channel circuit with a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium. The read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 8, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Xuebin Wu, Yang Han, Shaohua Yang
  • Memory system, method for controlling magnetic memory, and device for controlling magnetic memory
    Patent number: 9720772
    Abstract: A memory system according to an embodiment includes a plurality of magnetic nanowires, a read unit that reads data from the magnetic nanowires, a shift control unit that shifts domain walls in the magnetic nanowires, and a read control unit. The read control unit is configured to control the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, and when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, determines a misalignment in the data and correct the data based on the misalignment.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Sukegawa, Hiroshi Yao, Kohsuke Harada
  • Scan-based test architecture for interconnects in stacked designs
    Patent number: 9720041
    Abstract: Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 1, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer
  • Method and system for reliable data communications with adaptive multi-dimensional modulations for variable-iteration decoding
    Patent number: 9722633
    Abstract: In an advanced adaptive modulation and coding (AMC) scheme, the code rate and the parity-check matrix (PCM) for low-density parity-check (LDPC) codes are adapted according to modulation formats and variable-iteration receivers. The degree distribution for the PCM adaptation is designed by heuristic optimization to minimize the required SNR via an extrinsic information transfer (EXIT) trajectory analysis for finite-iteration decoding. The method uses dynamic window decoding by generating spatially coupled PCM for quasi-cyclic LDPC convolutional coding. The method also provides a way to jointly optimize labeling and decoding complexity for high-order and high-dimensional modulations.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: August 1, 2017
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventor: Toshiaki Koike-Akino
  • Flash memory system and operating method thereof
    Patent number: 9710327
    Abstract: An operation method of a flash memory system includes a hard decision decoding on a codeword and a soft decision decoding on an error message block. The hard decision decoding on a codeword and the codeword comprises message blocks encoded with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method. When the hard decision decoding fails, the error message block to which the hard decision decoding fails among a plurality of the message blocks is identified. Soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block is generated and the soft decision decoding on the error message block based on the soft decision information is performed.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: July 18, 2017
    Assignees: SK Hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jeong-Seok Ha, Dae-Sung Kim, Su-Hwang Jeong
  • Detection and handling of virtual network appliance failures
    Patent number: 9690683
    Abstract: In one aspect, a method is implemented on a host platform on which a hypervisor (aka Virtual Machine Manager) and a plurality of virtual machines (VMs) are running, the plurality of VMs collectively hosting a plurality of Software Defined Networking (SDN) and/or Network Function Virtualization (NFV) appliances that are communicatively coupled via a virtual network. A software-based entity running on the host platform is configured to monitor the plurality of virtual network appliances to detect failures of the virtual network appliances. In response to detection of a virtual network appliance failure, messages containing configuration information are implemented to reconfigure packet flows to bypass the virtual network appliance that has failed.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Brian Skerry, Adrian Hoban
  • Transmitting apparatus and interleaving method thereof
    Patent number: 9685980
    Abstract: The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: June 20, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-Joong Kim, Se-ho Myung
  • LDPC code matrices
    Patent number: 9680503
    Abstract: An LDPC parity check matrix, includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 13, 2017
    Assignee: Entropic Communications, LLC
    Inventors: Shaw Yuan, Zong Liang Wu, David Barr, Shachar Kons
  • Method, electronic device and controller for recovering array of memory cells
    Patent number: 9679656
    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: June 13, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Nai-Ping Kuo, Ken-Hui Chen, Chao-Hsin Lin
  • Method of offloading cyclic redundancy check on portions of a packet
    Patent number: 9680605
    Abstract: A method and apparatus are provided for computing a CRC value for a data stream packet with a modified portion and an unmodified portion extending a distance to the end of the data stream packet by computing a first CRC value from the unmodified portion, computing a second CRC value from the modified portion, adjusting the second CRC value based on a shift length equal to the distance of the unmodified portion to compute a perspective shifted second CRC value by using a fixed number of distance lookup table operations, and generating an updated CRC value from the first CRC value and perspective shifted second CRC value, thereby avoiding recalculating a complete CRC value based on an entirety of the data stream packet.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: June 13, 2017
    Assignee: NXP USA, Inc.
    Inventors: Eric Englert, Bernard Marchand, John F. Pillar
  • Method and apparatus for error control in 3D video transmissoin
    Patent number: 9680610
    Abstract: Methods and apparatuses for error control in 3D video transmission over wireless network are described. Cooperative Automatic Repeat re Quest(ARQ) is disclosed, which is based on the selective repeat ARQ with consideration of two factors: one is the interdependent relationship between the multiple components of the 3D video, e.g. the 2D video and its depth information in the 2D-plus-Depth format; and the other is time constraints of video frames/packets for continuous video playback. The disclosed cooperative ARQ allows the sender to control ARQ strength adaptively on a per-frame/per-packet basis.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 13, 2017
    Assignee: THOMSON LICENSING
    Inventors: Yan Xu, Lin Du, Jianping Song
  • NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages
    Patent number: 9672102
    Abstract: Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method includes applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method also includes determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Akira Goda, Pranav Kalavade, Charan Srinivasan
  • Method and apparatus for transmitting and receiving packet in a communication system
    Patent number: 9673933
    Abstract: A method for transmitting a packet in a communication system is provided. The method includes dividing a data stream into data payloads of a predetermined size and adding a common header to each of the data payloads, to generate a source payload, adding a first Forward Error Correction (FEC) payload Identifier (ID) to the source payload and applying an FEC code thereto, to generate an FEC source packet for a source payload, adding a second FEC payload ID to at least one parity payload and applying an FEC code thereto, to generate an FEC parity packet for the at least one parity payload, and transmitting the FEC source packet and the FEC parity packet.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hee Hwang, Kyung-Mo Park, Hyun-Koo Yang
  • Device and method for processing data using logical information and physical information
    Patent number: 9672105
    Abstract: A method of operating a data storage device includes generating at least one pseudo noise (PN) sequence using logical information and physical information for the data storage device. The method also includes converting first data into second data using the at least one PN sequence. The logical information may be a logical address for the data storage device, and the physical information may be a physical address for the data storage device.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Soo Chung, Jun Jin Kong, Hongrak Son, Pilsang Yoon, Seong Hyeog Choi