Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: A method for data communication between a first node and a second node over a data path includes determining one or more redundancy messages from data messages at the first node using an error correcting code and transmitting messages from the first node to the second node. The transmitted messages include the data messages and the redundancy messages. The method includes, receiving, at the first node, a first plurality of messages including messages indicative of a rate of arrival at the second node of the messages transmitted from the first node and messages indicative of successful and unsuccessful delivery of the messages transmitted from the first node to the second node. A first transmission limit and a second transmission limit are maintained according to the first plurality of messages. Transmission of messages from the first node to the second node is limited according to the maintained first transmission limit, and according to the second transmission limit.

Abstract: An optical transmission system includes a first optical transmission apparatus that adds a plurality of error correction codes to a main signal, retrieves, from a first error correction code that is added to the main signal and that corresponds to a first sub-carrier among the plurality of sub-carriers, a first code portion in excess of a predetermined redundancy level, distributes the first code portion to a second sub-carrier among the plurality of sub-carriers, concatenates a second code portion into the first error correction code, and transmits an optical signal including the main signal multiplexed with the first error correction code that has been concatenated with the second code portion.

Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data processing system. An illustrative data processing system includes a processing circuit that processes unprocessed codewords, and provides failed codewords when the processing fails to converge. The system may further include an input buffer circuit that selectively stores a combination of at least one of the unprocessed codewords and at least one of the failed codewords. The input buffer circuit includes a first portion that maintains any of the unprocessed codewords and the failed codewords, and a second portion that maintains only the failed codewords.

Abstract: One embodiment provides a method comprising, for at least one data block, selecting an erasure code from a plurality of erasure codes based on at least one property of the at least one data block and information relating to a data cache, and encoding, utilizing at least one hardware processor, the at least one data block with the selected erasure code. The information relating to the data cache includes cache space usage of the data cache.

Abstract: A memory access apparatus includes a read-write module and a processing module. The read-write module is configured to store an error detecting code in an (M+2)th DRAM in the memory row, and store the error correcting code in a Zth DRAM in the memory row, where Z is a positive integer, 1?Z?(M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. The processing module is configured to calculate one group of error detecting code for each single chip burst cluster (SCBC) in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row.

Abstract: A trusted boot device secures JTAG scan chains of integrated circuit components on a circuit card assembly without necessarily modifying the integrated circuit components. Component JTAG port I/O scan chain signal pins are independently routed to FPGA fabric on the trusted boot device. The trusted boot device monitors the JTAG paths and triggers a security event if unauthorized activity is detected on a JTAG path. JTAG paths on the secure trusted boot device are latch disabled by default and upon detection of a security event. JTAG paths are only enabled for a predefined length of time. To prevent JTAG access when protected data is exposed, a watchdog timer latch disables the JTAG paths when the predefined time has expired and may trigger a security event if activity is detected after the time has expired. A power cycle is then used to re-enable authenticated JTAG enable requests.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a test mode enable signal and a switch control signal and receives test data. The second semiconductor device generates first internal data and second internal data in response to the test mode enable signal, drives a first pad in response to the first internal data, drives a second pad in response to the second internal data, and drives a third pad in response to the first and second internal data according to the switch control signal.

Abstract: Disclosed are methods, systems, devices, apparatuses, computer-/processor-readable media, and other implementations for data communication in which data is divided into multiple data blocks, with each of the multiple data blocks including a portion of a respective at least one other of the multiple data blocks to produce multiple corresponding resultant data blocks. Additionally, at least one validation code is generated based on the multiple corresponding resultant data blocks. At least the multiple corresponding resultant data blocks and the at least one validation code are communicated to a remote device.

Abstract: A memory system or flash card includes a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects can be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements are used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements leads to improved memory management and data management. That action includes calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: Techniques for making storage of data objects eventually durable using redundancy encoding are described herein. Data objects are stored in a first set of data storage devices with a first durability. After a predetermined length of time, the data objects are converted to data shards and distributed to a second set of data storage devices with a second durability that is distinct from the first durability.

Abstract: In one example case, a cross-platform system includes a first automated test platform having a first test instrument and a first glue layer interface that exposes test functions to direct testing by the first test instrument. The system further includes a second automated test platform having a second test instrument and a second glue layer interface that exposes the same test functions to direct testing by the second test instrument. In the system, the glue layers abstract the respective and different control commands used by the different, first and second test instruments. Using the glue layers, the same higher-level test code can be executed by the control computers of both the first and second automated test platforms.

Abstract: A transmitting apparatus includes: a low density parity check (LDPC) encoder configured to encode information bits to generate parity bits based on a parity check matrix according to a code rate of 8/15 and a code length of 64800; an interleaver configured to interleave an LDPC codeword including the information bits and parity bits; and a mapper configured to map the interleaved LDPC codeword onto constellation points, wherein the parity check matrix comprises an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is defined by a specific table indicating indices of rows at which a value “1” is positioned in a 0-th column of an i-th column group in the parity check matrix.

Abstract: An operating method of an error correction decoder includes receiving data, setting initial log-likelihood values of variable nodes, and decoding the received data by updating a log-likelihood value of a selected variable node by use of a minimum value and a minimum candidate value associated with the selected variable node. The minimum value indicates a minimum value of absolute values of log-likelihood values of first variable nodes sharing a check node with the selected variable node and including the selected variable node. The minimum candidate value indicates one from among absolute values of log-likelihood values of second variable nodes that has the smallest value greater than the minimum value. The second variable nodes are selected later than one from among the first variable nodes corresponding to the minimum value.

Abstract: A hierarchical and flexible method for setting a memory reliability level to implement a memory access mechanism for different running object types and different reliability levels. The method implemented by the memory device includes receiving reliability level information of a running object of a processor sent by the processor; establishing a mapping relationship according to the reliability level information of the running object; receiving an access request sent by the processor; and accessing data of the running object and error-tolerant code of the running object according to the access request and the mapping relationship.

Abstract: A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main data, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.

Abstract: Provided is a data processing method which includes: encoding information word bits to generate parity bits based on a parity check matrix of a low density parity check (LDPC) code; interleaving a codeword comprising the input bits and the parity bits; and mapping the interleaved codeword into constellation points, wherein each of the constellation points corresponds to a modulation symbol, the parity check matrix is divided into a plurality of groups based on a number of bits included in the modulation symbol, and a sum of elements at a same position in each of the plurality of groups is less than 2.

Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword, and second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword that is written to the storage medium.