Abstract: An apparatus for polar coding includes an encoder circuit that implements a transformation c=u1N-sBN-s{tilde over (M)}n, where u1N-s, BN-s, {tilde over (M)}n, and C are defined over a Galois field GF(2k), k>1, N=2k, s<N, u1N-s=(u1, . . . , uN-s) is an input vector of N-s symbols over GF(2k), BN-s is a permutation matrix, {tilde over (M)}n=((N?s) rows of Mn=), the matrix M1 is a pre-defined matrix of size q×q, 2<q, N=qn and n?1, and C is a codeword vector of N-s symbols. A decoding complexity of C is proportional to a number of symbols in C. The apparatus further includes a transmitter circuit that transmits codeword C over a transmission channel.

Abstract: A memory controller includes a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data, a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information, at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme, and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.

Abstract: The present application discloses a method for processing a signal. An apparatus detects, according to a check relationship set during a forward error correction coding, that a phase jump occurs in a data segment of a signal, and a quantity of degrees of the phase jump, performs, according to the quantity of degrees of the phase jump, a phase correction on the data segment; after the phase correction, performs a confidence correction on the data segment; and after the confidence correction, performs a forward error correction decision decoding on the data segment on which the confidence correction has been performed and output the data segment.

Abstract: Systems for performing turbo product code decoding includes an error intersection identifier determining a set of one or more error intersections using a set of error-containing codewords, and updating, based at least in part on Chase decoding performed on the set of error-containing codewords, the set of error intersections to obtain an updated set of one or more error intersections, a bit location selector suitable for selecting, from the set of error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords, and a Chase decoder performing Chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

Abstract: A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

Abstract: A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is connected with the non-volatile memory. The controlling circuit includes a function storage circuit. The function storage circuit stores plural prediction functions. According to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit predicts a read voltage shift of the first block.

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.

Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.

Abstract: A control device that performs encoding of data to a code word and decoding from the code word to data by an error correction code is disclosed. The control device has an error correction function by which a correctable error is automatically corrected in the decoding. The control device includes an error correction processing unit which switches error correction codes based on a correction rate, which is outputted from a correction rate calculation unit, of every state so as to perform encoding from data to a code word and decoding from the code word to data and output correction information related to error correction. A lifetime calculation unit calculates a device lifetime which is a current remaining lifetime of a device based on a correction capability value of a current error correction code, a current correction rate, and a failure factor coefficient of a current operation state.

Abstract: A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: Embodiments generally provide techniques for data framing and error correction for communications on a link. Embodiments include receiving a stream of bits within a metaframe. Upon determining that a cyclic redundancy check (CRC) for a portion of the stream of bits is valid, the portion of the stream of bits is forwarded without performing forward error correction (FEC) decoding for the first portion. Upon determining that a CRC for the portion of the stream of bits is invalid, FEC decoding is performed for the portion before forwarding the portion of the stream of bits. Embodiments also include generating a metaframe for transmission over a link, and upon determining that a current measure of network throughput is less than a predefined threshold amount of network throughput, inserting one or more checkpoints into the metaframe to create different segments of the metaframe. The metaframe is then transmitted over the link.

Abstract: In an encoding method, data segments and encoding information which indicates encoding patterns each representing a set of data segments used for a predetermined encoding calculation are acquired. An encoded data piece is generated by performing the predetermined encoding calculation based on each encoding pattern, and is stored in the memory. A first encoding pattern for generating the encoded data piece is compared to a second encoding pattern for a next encoding calculation, and the next encoding calculation is performed by using the encoded data piece corresponding to the first encoding pattern when at least a part of the second pattern is common with the first encoding pattern.

Abstract: A transmitting device encodes information bits of a first type of information and a second type of information into a codeword. The transmitting device interleaves the encoded information bits of the first type of information according to a first interleaving pattern and the encoded information bits of the second type of information according to a second interleaving pattern, thereby changing an order of the encoded information bits of at least one of the first type of information and the second type of information in the codeword and generating an interleaved encoded information bit sequence. At least one of the first and the second interleaving pattern is designed to allow the information bits of a first type of information to be decoded without knowing a length of the codeword. The transmitting device then transmits the interleaved encoded information bit sequence to a receiving device.

Abstract: A method for transmitting packets by a transmitter in a wireless communication network and retransmitting the packets not received correctly by receivers is discussed. The method includes transmitting the packets to at least two receivers, receiving reception acknowledgement response signals including ACK or NACK signals for the packets transmitted to the receivers, analyzing patterns of the received reception acknowledgement response signals in accordance with a number of the ACK or NACK signals, differently index coding the packets which are not received correctly by each receiver, and retransmitting the index-coded packets.

Abstract: A circuit and a method for testing for faults in a circuit path. The circuit comprises a memory, a collar flop connected in parallel with the memory, and a feedback path in communication with the output of the memory and the input of the collar flop. The method comprises applying a fault test vector to logic in the circuit path to produce a fault test vector response, propagating the vector or the response through a memory in the circuit path, and capturing the response in a collar flop.

Abstract: A semiconductor device includes a test data interface, a first data interface, and a second data interface. The test data interface generates first test data and second test data from data inputted through a test pad in response to a test control signal and outputs failure information to the test pad in response to a read control signal. The first data interface generates first aligned data from the first test data or the second test data in response to the test control signal. The second data interface generates second aligned data from the second test data.

Abstract: A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, the ECC circuit, and a processor. The memory includes a user data region and a management region. The management region stores access information of each of blocks in the user data region as a management table. The value of the access information is either a first value indicating that the number of access times is 0 or a second value indicating that the number of access times is greater than or equal to 1. When the value of the access information of the block is the first value, the circuit checks and corrects an error of data read from the block. When the value of the access information of the block is the second value, the circuit does not check and correct an error of data read from the block.