Abstract: A method of battery management of an electronic device, the electronic device, and a non-transitory computer readable recording medium are provided. The method includes detecting, by the electronic device, that a battery management criterion is met, enabling at least one of a plurality of battery management functions, in response to detecting that the battery management criterion is met, and performing at least one action corresponding to the enabled at least one of the plurality of the battery management functions.

Abstract: Embodiments include validating a user for performing a service procedure for a system and customizing the system for the user for the service procedure. An example computer-implemented method includes validating authorization of the user based on authentication data from a tag uniquely identifying the user. The method further includes receiving attribute data for the user from the tag. The method further includes generating and/or adapting a set of service procedure instructions that are customized for the user based on the attribute data. The method further includes displaying the set of service procedure instructions that are customized for the user.

Abstract: Host interface devices are provided. A host interface device includes a first pin connected to a first node and a second pin connected to a second node. The host interface device includes a switch connected between the second node and a first voltage terminal, and configured to provide a voltage from the first voltage terminal to the second pin in response to a voltage level of the first node. The host interface device includes a pull-up resistor connected between the first node and a second voltage terminal. Moreover, the host interface device is configured to receive a memory detection signal from a storage device via the first pin when the first pin is electrically connected to the storage device.

Abstract: An application power controller controls power supplied from rechargeable battery packs to a set of aircraft in-flight processing systems that are executing applications. Operations access a repository of application information to obtain a list of applications to be executed by the aircraft in-flight processing systems and power consumption information for the applications. Further operations obtain information from the battery monitor indicating health and capacity of the battery packs. The operations initiate an application deactivation action based on determining that the indicated health and/or capacity of the battery packs does not satisfy a battery protection rule defining constraints on battery usage. The operations then select one of the applications from among the list that is to be deactivated responsive to the application deactivation action, and communicate a command to at least one of the in-flight application processing systems to trigger the selected application to cease being executed.

Abstract: A communication node in a vehicle network may comprise a medium access control (MAC) layer; a physical (PHY) layer; a first port connected to the PHY layer; a second port connected to the PHY layer; and a switch controlling a connection between the first port and the second port. The switch may turn on or off the connection between the first port and the second port under control of the MAC layer.

Abstract: Technology to dynamically throttle power in a power delivery system is described. In one embodiment, a power delivery system includes a controller associated with a port to supply power. The controller manages a power budget available to the port based on a current state of one or more system parameters. The power budget available to the port can be throttled when the power delivery system operates under stress conditions and adjusted when the power delivery system is no longer operating under stress conditions.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract: An information handling system real time clock (RTC)/CMOS circuit is powered from a battery that powers the information handling system. The battery power is supplied through a power management circuit that manages power constraints to the real time clock and that protects the battery from exceeding current and voltage thresholds. A protection integrated circuit selectively cuts off power supply from a power module to the RTC/CMOS circuit if predetermined conditions are detected. The protection circuit may also cutoff all power from battery with a permanent failure option or may itself directly supply power to the real time clock/CMOS circuit.

Abstract: A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

Abstract: Embodiments support establishing an embedded controller comprised within an Information Handling System (IHS) as a hardware root of trust. With the booting of the IHS paused and based on instructions encoded in a ROM (Read-Only Memory) of the embedded controller, the firmware of the embedded controller is read from a flash memory, such as a SPI Flash, and stored to a RAM (Random Access Memory) of the embedded controller. The firmware is then authenticated based on instructions encoded in the ROM. Based on instructions included in the authenticated firmware, the embedded controller reads SBIOS (Startup Basic Input Output System) instructions from the flash memory and stores them to RAM where they are authenticated based on instructions included in the authenticated embedded controller firmware. If the SBIOS instructions are authenticated, the embedded controller authorizes booting of the IHS to resume using the authenticated SBIOS instructions.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Abstract: The time required for transition from an on-state to a suspend state is reduced. An electronic apparatus includes: a memory and a memory; a current control unit that performs a control to shut off supply of current to the memory; and a memory management unit that allocates a memory region in either the memory or the memory based on preference information indicating a memory region that needs to be preferentially allocated in the memory. For example, the preference information includes association with a first priority as a degree at which a memory region to be used by an application needs to be preferentially allocated in the memory, and when receiving a request of allocation of the memory region from the application, the memory management unit more preferentially allocates the memory region in the memory as the first priority associated with the application in the preference information is higher.

Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes determining, for a first sector from multiple sectors of a clock mesh of a semiconductor circuit, a set of mesh wires. The method further includes generating tapping point candidates, selecting a first combination of tapping points, and performing an analog electrical simulation of a clock signal. The simulation includes feeding the clock signal into the clock mesh via the first combination of tapping points via a clock signal transmitter, and measuring delays for the clock signal to reach a set of measuring nodes. The maximum delay from the measured delays is selected, and, in response to the maximum delay being less than a previous delay value, the first combination of tapping points is used to connect sector buffers from the first sector to the clock mesh.

Abstract: An example method for adjusting operation of an integrated circuit includes testing a plurality of electronic elements of the integrated circuit including one or more redundant electronic elements designated as inactive according to a manufacturer's default configuration of the integrated circuit to determine one or more operating parameters of the integrated circuit. The method further includes selecting a subset of electronic elements from the plurality of electronic elements based on the one or more operating parameters, wherein the subset of electronic elements is designated as active according to an updated configuration of the integrated circuit, and controlling operation of the integrated circuit using the updated configuration instead of the manufacturer's default configuration.

Abstract: A power source equipment (PSE) controller exhibiting low standby levels for power over Ethernet (PoE) includes a micro-controller, a detection and classification circuitry coupled to the micro-controller to detect if a powered device (PD) is connected and determine power needed to operate the connected PD, a power control and monitor circuitry coupled to the micro-controller to power the connected PD and to monitor the power consumption of the PD. The detection and classification circuitry, the power control and monitor circuitry can be individually turned off by the micro-controller to minimize standby power, the micro-controller can be put into deep sleep if no PD is detected or can be come out of deep sleep if a PD is detected.

Abstract: A terminal performs communication with an in-vehicle device to control a vehicle. The terminal includes a controller configured to switch and set a plurality of operation modes, and a vibration detection unit configured to detect vibration of the terminal. The operation modes include a first mode, a second mode different from the first mode, and a third mode where communication with the in-vehicle device is more restricted than in the first mode and the second mode. The controller is configured to, when the first mode is executed, in a case where vibration is not detected in the vibration detection unit for a predetermined time, switch the operation mode to the third mode, and when the second mode is executed, in a case where vibration is not detected in the vibration detection unit for a time longer than the predetermined time, switch the operation mode to the third mode.

Abstract: An information handling system includes first and second power supplies. The first power supply unit provides power to a power rail to power a load of the information handling system, and is configured to provide the power to the power rail at a first peak current level and at a first constant current level. The second power supply unit provides power to the power rail, and is configured to provide the power to the power rail at a second peak current level and at a second constant current level. The second peak current level is greater than the first peak current level, and the second constant current level is greater than the first constant current level.

Abstract: A system and method for synchronizing multiple integrated circuit (IC) chips for an input device having a display device integrated with a capacitive sensing device. A first one of the IC chips is a master IC chip and a second one of the IC chips is a slave IC chip. The master IC chip is configured to transmit synchronization signals to and from the slave IC chip, such that capacitive frames are acquired by each of the IC chips at substantially the same time, the initiation of the sensing signals is synchronized for each of the IC chips and the clock signals of the slave IC chips are synchronized with the clock signal of the master IC chip.