Abstract: An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

Abstract: A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Abstract: An oscillator includes a common logic circuit and a plurality of delay lines. Each delay line is configured to receive a state transition at its input terminal and to output a corresponding state transition at its output terminal after a corresponding delay. An output terminal of each delay line is in electrical circuit with a corresponding input terminal of the common logic circuit, and the input terminal of each of the delay lines is in selectable electrical circuit with the output terminal of the common logic unit. The common logic circuit is configured to output a state transition at its output terminal in response to a state transition at any one of the input terminals of the common logic circuit.

Abstract: A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an input clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and falling edges of the input clock signal.

Abstract: The present invention provides a modulator which has a high degree of modulation and a good modulation sensitivity. The modulator comprises an oscillating circuit and a resonator portion, and this resonator portion comprises a reflective circuit board, a coupling line which is disposed on the reflective circuit board, a coupled load which is coupled to one end of the coupling line, a dielectric resonator which is disposed on the reflective circuit board and which is magnetically coupled with the coupling line, a window portion which is formed in the undersurface of the reflective circuit board directly beneath the coupling line, a waveguide resonator which is disposed on the undersurface of the reflective circuit board in the area that includes the window portion, and which is magnetically coupled with the coupling line, and a varactor diode which is inserted between the opposite signal conductor surfaces and of the waveguide resonator, and to which the input modulating signal terminal is connected.

Abstract: A tuning circuit for use in tuning multiple voltage-controlled oscillators (VCOs) of a phase-locked loop (PLL) is provided. A search algorithm is used to determine which VCO to use for a given frequency to be synthesized by the PLL. The tuning circuit provides a binary representation, associated with the frequency to synthesize, to the PLL. The PLL responds to this representation by attempting to synthesize the associated frequency. New binary representations are provided until an indication of a threshold frequency between multiple VCOs is determined. A record of the threshold frequency is stored. The binary representation of a frequency to be synthesized and the stored record of the threshold frequency are used to provide an indication of which VCO of the PLL to use to synthesize the desired frequency.

Abstract: In a method for demodulating an analog FSK signal (FSKin), a current sample (Id(k);Idi) of the downconverted and digital inphase component is multiplied with a previous sample (Qd(k−1);Qdi−1) of the downconverted an digital orthogonal phase component. The product thereof is subtracted from the product obtained by multiplying a current sample of said orthogonal phase component (Qd(k); Qdi) with a previous sample (Id(k−1); Idi−1) of said inphase component. Said current and said previous samples of said inphase and said orthogonal phase components are spaced apart by the digital baseband signal period. In a variant method said current sample and said previous sample of said inphase and orthogonal phase component are spaced apart by an integer fraction (n) of said digital baseband signal period,whereby the steps of said method are repeated, thereby further adding consecutive values of the result Ri).

Abstract: A frequency sythesizer and a method for synthesizing a signal having a given output frequency includes providing a controlled oscillator having a frequency control input and a feedback loop, applying a frequency control signal to the frequency control input, and compensating gain variation of the controlled oscillator outside of the feedback loop.

Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that would utilize this square wave clock signal.

Abstract: A feedback circuit and amplifiers using a vibrator comprising a piezoelectric body having a bismuth layered compound as the main ingredient thereof are provided so as to generate oscillation. Load capacitors comprising the feedback circuit together with the vibrator are formed. These load capacitors each have, as the main ingredient thereof, a dielectric body which decreases in the relative dielectric constant with the increase in temperature in the region not less than one half the temperature range from −20 to 80° C., and in which the &egr;-TC is not less than 5000 ppm/° C., wherein the &egr;-TC is an average change rate of the relative dielectric constant in the above-described temperature range and is represented by (Cmax−Cmin)/(C20·100), where Cmax is the maximum value of capacitance in the above-described temperature range, Cmin is the minimum value of capacitance in the above-described temperature range, and C20 is the capacitance at 20° C.

Abstract: The invention provides an improved high speed voltage controlled oscillator (VCO) buffer cell, with consistent output performance. According to one embodiment of the invention, the cell comprises a differential pair of transistors and a current mirror circuit. The differential pair has input terminals for receiving input signals and output terminals for providing differential voltage swing in response to the input signals. The current mirror circuit is operably coupled to the pair of transistors and is configured to receive a first external reference current and provide a mirrored current to an active one of the transistors. The differential voltage swing has a frequency which is determined based on the reference current. In a specific embodiment of the invention, the pair of transistors of the cell is bipolar transistors, and the current mirror circuit is composed of CMOS transistors.

Abstract: A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: A modification of the synchronous oscillator is described, having regenerative positive feedback. The circuit includes an amplifier, a high-Q tank circuit, and a conventional synchronous oscillator feedback network. An additional feedback path provides a negative impedance conversion effect.

Abstract: A single mode state machine for recovering the Universal Serial Bus (USB) clock from the USB. The claimed state machine running at 4X speed includes only five states and generates a 1X speed clock. When transmitting, the claimed invention acts as a divide-by-four counter and divides the 4X clock into a 1X clock to be used by control logic (for example, a Serial Interface Engine). When receiving, the same state group acts as a divide-by-four counter with the received data's status being continuously monitored to reset the state machine to an original state to dynamically adjust the duty cycle of the receiving clock. The exact selection of transition path is determined by the logical AND of a phase change within the data and a signal indicating whether the state machine is currently transmitting or receiving.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: An oscillator circuit with connectable capacitance makes it possible for the oscillator to change over between at least two frequencies. A switching unit is provided for the changeover. The switching unit has a first switch which is connected between the switchable capacitances, and also further switches, which are connected with respect to a supply voltage terminal. Compared with conventional oscillators that can be changed over, the novel circuit provides for the advantage that a particularly low forward resistance takes effect in the switched-on state of the connectable capacitances and particularly small parasitic capacitances nevertheless take effect in the switched-off state. The oscillator circuit can be implemented with a particularly small chip area since the switches can be integrated in a common transistor structure with a common control terminal. The oscillator circuit is particularly suitable for mobile radio applications.

Abstract: An apparatus comprising a first oscillator, a second oscillator and a logic circuit. The first oscillator circuit may be configured to generate a first clock signal. The second oscillator circuit may be configured to generate a second clock signal. The logic circuit may be configured to generate an output clock signal by selecting either the first clock signal or the second clock signal.

Abstract: The invention is a radio transmitter and a method for transforming digital amplitude as well as phase or frequency modulation information into analog signals for controlling analog amplifier circuitry. The method includes providing first and second digital signals representing phase angle; converting the signals into analog signals; mixing the analog signals with oscillator signals to obtain an analog, modulated signal; providing a third digital signal corresponding to amplitude; converting this signal into an analog signal; and feeding the analog, modulated signal and said analog signal to the analog amplifier circuitry.

Abstract: The present invention relates to n-port junction devices for processing modulated digital RF signals, n being an integer larger than 3, the n-port junction device comprising two RF input ports (4, 5), two passive signal-combining means (2, 3) connected to each other wherein respectively one of the passive signal-combining means (2, 3) is connected to one of the RF inputs (4, 5), and at least two power sensors (P1, P2) wherein each of the passive signal-combining means (2, 3) has at least an output port (6, 7) and each output port (6, 7) is connected to a power sensor (P1, P2). The two passive signal-combining means (2, 3) are connected with each other by means of a phase shifting element (10).