Abstract: A phase locked loop (10) for generating an output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the output frequency signal in response to a tune signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. The loop filter (12) includes a bandwidth switching circuit (19) to vary the filter characteristics. A charge cancellation circuit (22) is coupled to the loop filter (12). In response to the error signal, the charge cancellation circuit (22) cancels errors associated with the bandwidth switching circuit.

Abstract: A microcontroller is disclosed that includes a crystal oscillator circuit that is programmable to provide multiple different levels of startup current. In the present embodiment, the crystal oscillator circuit includes logic devices for receiving programming indicating one of a plurality of different startup current levels and a resistor chain. The logic devices are coupled to the resistor chain for controlling the resistance of the oscillator circuit such that, upon receiving programming indicating a particular startup current level, the crystal oscillator circuit generates a corresponding startup current. In addition, the crystal oscillator circuit includes provision for selecting one of a plurality of different levels of capacitance. Furthermore, the crystal oscillator circuit includes a pass gate that includes circuitry for assuring predetermined startup conditions are met. A feedback loop that includes an amplifier provides for steady-state operations that have low power consumption.

Abstract: A miniature ovenized crystal oscillator has a ceramic case that has a cavity, a bottom and a ledge that extends into the cavity. The case has several circuit lines. A substrate is located in the cavity and is supported by the ledge. The substrate has a top and bottom surface and several circuit lines. A crystal is mounted to the bottom surface of the substrate and is connected to the substrate circuit lines. A signal conditioning circuit is mounted to the top surface of the substrate and is connected to the substrate circuit lines. The case circuit lines are connected to the substrate circuit lines by a conductive epoxy. A heater is mounted to the bottom of the ceramic case. A thermal adhesive is located between the heater and the crystal. The thermal adhesive thermally links the crystal and the heater.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a reference input and a feedback signal. The second circuit may be configured to generate the feedback signal according to a plurality of moduli in response to the output signal, a first control signal and a second control signal. The frequency of the output signal may be modulated in response to the second control signal.

Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.

Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.

Abstract: A coin validator tests a coin using a pair of coils coupled in an oscillator circuit which is arranged to drive both the coils concurrently at two separate frequencies without interference therebetween, each frequency signal being influenced by the presence of a coin. Preferably, the coils are connected in series in a feedback loop to form a first oscillator, and the second oscillator is coupled to the interconnection between the coils the other ends of which are effectively short circuited at the frequency of the second oscillator.

Abstract: A switching transistor is connected to a primary winding of a transformer, an oscillation frequency control circuit is connected to a feedback winding, the oscillation frequency control circuit controls a first controlling transistor, and the first controlling transistor controls the delay time when the switching transistor is turned on. The oscillation frequency control circuit is set in a first operation mode in which the above delay does not take place at the rated load, in a second operation mode in which the oscillation frequency is controlled such that the oscillation frequency becomes constant or slowly decreases at light loading and in a third operation mode in which the oscillation frequency is further decreased while a switch is switched on.

Abstract: An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.

Abstract: A phase-locked loop circuit is described and has a digital circuit section and an analog circuit section that are fed with different supply voltages. Control signals generated by the digital circuit section are conducted to the analog circuit section via level converters and therefore can control functions in the analog circuit section.

Abstract: A high-frequency crystal oscillator capable of outputting a signal at a frequency, for example, higher than 500 MHz without using a multiplication amplifier. The high-frequency crystal oscillator comprises a voltage controlled Colpitts oscillation circuit operating at the fundamental frequency of a quartz-crystal element, means for increasing the level of harmonic component in an output from the Colpitts oscillation circuit, an SAW (Surface Acoustic Wave) filter for selecting a component of a predetermined order of the harmonic component, and a broadband amplifier for amplifying the component selected by the SAW filter. The means for increasing the levels of harmonic component is, for example, a resistor for setting the operating point of a transistor in the oscillation circuit such that an output signal is distorted.

Abstract: An oscillating element, particularly for a level sensor, comprises an oscillating diaphragm (3), a stack of piezoelectric elements (6, 7), and a tie bolt (4) connected to the diaphragm (3) for pressing the piezoelectric elements (6, 7) against the diaphragm (3). The tie bolt (4) forms a single piece with the diaphragm (3).

Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.

Abstract: A crystal oscillator circuit is disclosed including a differential amplifier, a positive feedback assembly, and a series resonant crystal assembly. The differential amplifier includes a first transistor and a second transistor. The positive feedback assembly is coupled to each of the first and second transistors, and has a loop gain of greater than unity. The series resonant crystal assembly is coupled to one of the first and second transistors, and includes a crystal and a capacitor.

Abstract: All PMOS (p channel metal oxide semiconductor) fully differential voltage controlled oscillator (VCO). A fully differential implementation within the present invention provides for a very effective rejection of common mode noises. In addition, the PMOS implementation of the present invention allows for a substantial reduction in 1/f noise. The PMOS fully differential VCO may be employed within phase locked loops (PLLs) and other applications that require a very clean signal (with very low noise) and that must be operable at very high frequencies. The present invention enables a very compact design, thereby minimizing extraneous noise pickup. The device may be over-driven with a higher power supply than is commonly used in prior art VCOs; the over-driving provides for a higher transconductance gm from the PMOS device enabling higher gain. A center-tapped inductor is shunted to ground in a manner that does not reduce the inductor's quality factor Q.

Abstract: A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase comparison circuit through a split loop filter. The oscillator has two varactors in parallel in its tuning circuit. The first branch of the loop filter includes an integrator filter generating a first error voltage and the second branch includes a low pass filter generating a second error voltage. The first error voltage controls one varactor and the second error voltage controls the other varactor. As a result the error voltages are effectively summed in the capacitance domain to obviate the need for a dedicated error voltage adder and to allow the total capacitance required in the loop filter to be reduced while still retaining an adequate signal to noise ratio in the filter.

Abstract: Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.

Abstract: A voltage-controlled oscillator includes a multilayer substrate having two grounding electrodes. A bare chip IC, a grounding capacitance connected to the collector of a transistor in an oscillator stage disposed in the IC, an electronic component, and other elements, are mounted on one surface of the multilayer substrate, and the electronic components are connected by an electrode pattern. A microstrip line electrode is disposed between the grounding electrodes inside the multilayer substrate, and the collector of the transistor and the capacitor disposed in the IC are connected by through-holes. A sealing resin is filled between the IC and the multilayer substrate to maintain the mounting strength of the IC. A space is provided between the IC and the capacitor to prevent adhesion of the sealing resin to the grounding capacitance.

Abstract: A Phase-locked Loop (PLL) (204) that is dynamically and automatically altered in response to changes in the jitter of the input is disclosed. The Analysis Block (304) receives one or more inputs from the PLL operation. The output of the Analysis Block (304) triggers a change in the Parametric Control Block (308) which in turn imparts changes on the gains of one or more of the various components or the value of &ohgr;N of the PLL Low Pass Filter (116). The dynamic change to at least one parameter of the PLL adjusts the tradeoff between removing as much of the jitter as possible and having a responsive system that has a reduced risk of buffer underflow or overflow. This abstract is provided as a tool for those searching for relevant disclosures, and not as a limitation on the scope of the claims.

Abstract: A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.