Abstract: A phase locked loop in an imaging system is used to generate signals on one of eight equal phase steps within a clock period. The phase locked loop outputs eight clock phases, or four clock phases and their complements, each running at the pixel rate, eliminating the need for higher speed circuitry. According to one embodiment, the phase locked loop employs an oscillator with three inverting stages and one non-inverting stage. The output of each stage is shifted in phase 45 degrees from the previous one, in terms of pixel clock rate. Differential stages are employed so that the delay of the inverting and non-inverting stage are the same. According to the present invention, the output of the last stage is swapped onto the input of the first stage, making it non-inverting without path delay, permitting oscillation with each stage's output remaining at 45 degrees of the previous stage's phase.

Abstract: Direct up-conversion of a signal is accomplished using a sampling pulse generator circuit and a gated differential amplifier, enabled by the sampling signal. When not enabled, the output of the differential amplifier is pulled to zero. The sampling pulse is generated from a base frequency sine wave which is squared with a limiting amplifier, and further passed through one or more frequency doublers producing a times two signal, a times four signal and so on. The squared base frequency and frequency doubled signals are logically ORed to produce a short duration pulse which repeats at the frequency of the base signal. The resulting output is an amplitude modulated pulse doublet time domain waveform.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: One embodiment of the present invention is a programmable clock architecture for a microcontroller that provides multiple different clocking signal frequencies that may be utilized by one or more programmable logic blocks of the microcontroller. In this manner, the clocking architecture enables the programmable logic blocks to perform a wider variety of functions because they have access to a wider variety of clock signal frequencies. Specifically, the clocking architecture of the present embodiment includes a plurality of clocking sources. For example, the output clocking signal of one of the clock oscillators is divided down to different smaller frequencies and also multiplied to provide more frequencies that may be utilized by the programmable circuit blocks and processor of the microcontroller.

Abstract: A non-linear phase detector includes a retiming stage and a phase synchronization stage. The retiming stage is coupled to a data signal and a recovered clock signal. The retiming stage is triggered by the recovered clock signal and samples the data signal to generate a retimed data signal and a clock synchronization signal. The phase synchronization stage is coupled to the retimed data signal and the clock synchronization signal. The phase synchronization stage is triggered by the retimed data signal and samples the clock synchronization signal to generate a phase control signal.

Abstract: A voltage controlled oscillator includes an oscillation controller, first and second current sources, oscillation section, and first and second fluctuation transmitters. The oscillation controller generates first and second control potentials. The first and second current sources generate control currents corresponding to the first and second control potentials, respectively. The oscillation section is connected to a power source potential node via the first current source and connected to a ground potential node via the second current source, and generates a clock. The first fluctuation transmitter is disposed between the power source potential node and the first control potential node, and transmits a potential fluctuation in the power source potential node to the first control potential node.

Abstract: There are provided a stable and highly sensitive nanometric mechanical oscillator having a considerably high detection resolution that enables detection of variation in force or mass on the nanometer order, as well as a method of fabricating the same, and a measurement apparatus using the same. A nanometric mechanical oscillator (10) includes a base (11), a tetrahedral oscillator mass (13); and an elastic neck portion (12) for connecting the base (11) and the tetrahedral oscillator mass (13). The oscillator (10) assumes a mushroom-like shape and has a nanometric size. The oscillator mass (13) assumes a tetrahedral shape and is suitable to be used as a probe of a scanning forth microscope in which the oscillator mass (13) serving as a probe is caused to approach to an arbitrary sample surface in order to observe the surface state.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract: An improved temperature compensated quartz oscillator, which includes a package for mounting compensating circuitry over a cavity instead of on a planar layer, reduces the chip failure rate by preventing undesired contact of the compensation circuitry with the material forming the layer upon which the circuitry is mounted.

Abstract: A FM demodulator using a single input signal has two I-Q splitters with constant group delay apparatuses. During operation, t two I-Q splitters with constant group delay apparatuses may receive the input modulated signal to generate not only one pair of modulated and respectively delay &tgr;1 and &tgr;2 in phase signals but also another pair of modulated and respective delay &tgr;1 and &tgr;2 quadrature signals. These signals are used to demodulate the final demodulated signal.

Abstract: A circuit that synchronizes an output clock signal to a second clock signal includes a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output signal clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal.

Abstract: This temperature-compensated crystal oscillator includes: a temperature sensor 11; an analog type temperature compensating section 12; a digital type temperature compensating section 13; an adder circuit 14; and a voltage controlled crystal oscillating circuit 3. The analog type temperature compensating section 12 and the digital type temperature compensating section 13 each generate temperature compensation voltages based on an input voltage corresponding to the temperature detected by the temperature sensor 11. Both of these temperature compensation voltages are added to each other by the adder circuit 14 and the resultant added voltage is applied to a voltage control terminal of the voltage-controlled crystal oscillating circuit 3. Thereby, an oscillation frequency of the voltage-controlled crystal oscillating circuit 3 is stabilized, resulting in realization of the temperature compensation of a crystal resonator 4.

Abstract: The invention relates to a demodulator and a demodulation method for a TFM-modulated signal comprising symbols, the method comprising the steps of calculating an estimate for the symbols, determining an estimate for the phase shift, determining a modulation index estimate error using the phase shift and the symbol estimates and removing the estimated error from the modulation index estimate using the symbol estimates.

Abstract: An RF Voltage Controlled Oscillator (VCO) design having improved power supply noise immunity. More particularly, a VCO resonant circuit that provides a high circuit Q, immunity to noise, and is tunable over multiple distinct bands. The resonant circuit is implemented in conjunction with an integrated circuit oscillator that requires a tuned circuit to determine the frequency of operation. When the integrated circuit oscillator is used as a Local Oscillator (LO) within a wireless phone it is subjected to numerous sources of power supply noise. In a Code Division Multiple Access (CDMA) wireless phone system the power supply to portions of the RF transmit path are cycled on and off depending on the transmitted data rate. The present invention provides an oscillator with increased immunity to the noise induced on the power supply due to power supply cycling.

Abstract: A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) having a parallel resonant circuit including a first capacitance implemented by a reverse-biased diode and a second capacitance implemented by MOS capacitors. Upon lock-in of the oscillation frequency with respect to the reference frequency, whether the oscillation frequency has a deviation is examined based on the tune voltage controlling the first variable capacitance. If a deviation is observed due to a temperature fluctuation etc., the control voltage for the second variable capacitance is corrected for compensating the deviation.

Abstract: A vibrating piece comprises a base and vibrating arms formed protruding from the base, wherein a groove is formed on at least one of the front side and rear side of the vibrating arms, and wherein notches are formed in the base.

Abstract: A circuit and method for assuring rapid initiation of resonant oscillation of an electromechanically oscillatory system driven by phase lock loop circuits. An open loop starting signal commences driving of the object at a starting frequency above the resonant frequency. The starting signal reduces the drive frequency until the resonant frequency of the system is reached and the starting signal is removed.

Abstract: A demodulating circuit for use in contactless integrated circuit cards and systems, the demodulating circuit receiving an input signal, biasing the input signal by a preselected voltage, amplifying the signal such that is becomes half-wave rectified, and removing a modulation signal component from the signal, thereby demodulating the signal in a simple and efficient manner.