Abstract: A light-emitting chip holder includes a conductive base and a casing. The conductive base includes pad pairs spaced along a first direction, and each pad pair includes a connection pad and a bonding pad spaced along a second direction different from the first direction. The connection pad includes a main portion and an extension portion. The bonding pad includes first and second bonding portions. The casing forms concave groups on a side of the conductive base. The concave group includes first and second concaves adjacent to each other in the second direction. The pad pairs includes adjacently arranged first and second pad pairs. In each the concave group, the first pad pair and the second pad pair are arranged in a centrosymmetric manner. A flexible series-connection and/or parallel-connection design for light-emitting devices can be conveniently realized.

Abstract: A semiconductor chip (2) is provided on an upper surface (1a) of a heat sink (1). A lead terminal (5,6) is electrically connected to the semiconductor chip (2), does not extend above a first side surface (1c) of the heat sink (1) but extends above a second side surface (1d) of the heat sink (1). Mold resin (10) covers them. A lower surface (1b) of the heat sink (1) is exposed from the mold resin (10). An anchor structure (11) in which a lower portion of the first side surface (1c) of the heat sink (1) is recessed and is filled with the mold resin (10) is provided. The anchor structure (11) does not exist on the second side surface (1d) of the heat sink (1). The heat sink (1) does not protrude from a side surface (10a) of the mold resin (10).

Abstract: A manufacturing method includes performing imposition on at least two discrete double-side packaged structures such that lateral electrical connection structures located on the same side of each of the at least two discrete double-side packaged structures are coplanar; and electrically mounting a first component onto lateral electrical connection structures on the first side, where a double-side packaged structure includes a substrate, the lateral electrical connection structures are formed on the first face and the second face of the substrate, and the first face is opposite to the second face and is adjacent to the first side.

Abstract: A display device comprises a first conductive layer on a substrate including gate electrodes and 1-1th and 2-1th connecting conductive patterns; a second conductive layer on the first conductive layer including source electrodes and drain electrodes and 1-2th and 2-2th connecting conductive patterns; bank patterns on the second conductive layer, extending in first and second directions intersecting each other, and surrounding subpixels; a first electrode on a first bank pattern disposed in each of the subpixels to extend in the first direction; second electrodes on second bank patterns spaced apart from each other with the first electrode being disposed between the second electrodes and extending in the first direction; light-emitting elements disposed on the first electrode and the second electrodes; a first connecting electrode disposed on the first electrode and contacting first light-emitting elements; and a second connecting electrode disposed on the second electrodes and contacting the second light-emit

Abstract: An electronic device is disclosed. The electronic device includes a carrier, an optical component disposed on the carrier and a humidity indicator within the electronic package. A position of the humidity indicator within the electronic package is arranged such that at least a part of the humidity indicator is visible from a viewpoint outside of the electronic package.

Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Abstract: The present invention relates to a semiconductor device including: a semiconductor substrate having: an active region through which a main current flows; and a termination region around the active region; a polyimide film disposed in the active region and the termination region; and a passivation film disposed as a film underlying the polyimide film, wherein the termination region includes, in order from a side of the active region, a breakdown voltage holding region and an outermost peripheral region, the polyimide film is disposed except for a dicing remaining portion of the outermost peripheral region, and the passivation film is disposed, as the underlying film, at least in a region where the polyimide film is disposed.

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a redistribution circuit structure. The semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure includes conductive patterns, wherein the conductive patterns each comprise a first portion, at least one second portion, and at least one connecting portion. A first edge of the at least one connecting portion is connected to the first portion, and a second edge of the at least one connecting portion is connected to the at least one second portion, wherein the first edge is opposite to the second edge, and a length of the first edge is greater than a length of the second edge.

Abstract: The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

Abstract: A semiconductor substrate includes: an active region; and a termination region surrounding the active region, and the semiconductor device includes: a first main electrode provided on the active region; a second main electrode provided on an opposite side of the first main electrode; an impurity region provided on an outermost periphery of the termination region; a first insulating film provided on an outer end edge part; a second insulating film provided on a region from an inner end edge part of the termination region to an end edge part of the active region; a first semi-insulating film covering a region from part of the impurity region which is not covered by the first insulating film to a partial upper side of the first insulating film; and a second semi-insulating film covering a region from the first semi-insulating film to a partial upper side of the first main electrode.

Abstract: Disclosed is a semiconductor device comprising a substrate including a peripheral region and a logic cell region, a first channel pattern including a first and a second semiconductor pattern stacked vertically on the peripheral region, a first gate electrode across the first channel pattern and extending in a first direction, a second channel pattern including a third and a fourth semiconductor pattern stacked vertically on the logic cell region, and a second gate electrode across the second channel pattern and extending in the first direction, the second gate electrode having a second width in a second direction less than a first width in the second direction of the first gate electrode. The first gate electrode has a first thickness between the first and the second semiconductor pattern, and the second gate electrode has a second thickness between the third and the fourth semiconductor pattern greater than the first thickness.

Abstract: A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.

Abstract: A stable, hermetically sealed, partially optically transparent package for use to protect optoelectronic components is provided. The package has good cooling for the installed circuit elements and is as stable in relation to temperature and UV. The package has a cap with a frame made of a nitride ceramic and a glass element. The frame has an opening and the glass element hermetically closes the opening. The glass is fused onto the nitride ceramic and is fixed in contact with the nitride ceramic of the frame.

Abstract: A method includes rolling a roller with a protrusion across a lead frame to create an indent in a feature of the lead frame, attaching a die to a die attach pad of the lead frame, coupling the die with a lead, and enclosing portions of the die, the die attach pad, and portions of the lead frame feature with a molding compound. A system includes a roller with a cylindrical body and a protrusion, a chuck to engage a lead frame, and a controller to roll the roller across the lead frame to create an indent in a feature of the lead frame. An integrated circuit includes a package structure enclosing a first portion of a lead and a first portion of a die attach pad, and a rolled indent in the first portion of the lead or the die attach pad.

Abstract: An LED-filament comprising: a partially light transmissive substrate; a plurality of LED chips on a front face of the substrate; a photoluminescence material that is in direct contact with and covers all of the plurality of LED chips; and a light scattering layer that is in direct contact with and covers at least the photoluminescence material, wherein the light scattering layer comprises particles of light scattering material, and wherein the photoluminescence material comprises broadband green to red photoluminescence materials and narrowband red photoluminescence material.

Abstract: A resonance device that includes a MEMS substrate that includes a resonator, a top cover having a silicon oxide film on a surface thereof that faces the MEMS substrate, and a bonding part that bonds the MEMS substrate and the top cover to each other so as to seal a vibration space of the resonator. The silicon oxide film includes a through hole that is formed along at least part of the periphery of the vibration space when the top cover is viewed in a plan view and that penetrates to a surface of the top cover. The through hole includes a first metal layer.

Abstract: A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.