Abstract: An image sensing device includes a photoelectric conversion element configured to generate photocharges in response to incident light, a floating diffusion configured to temporarily store the photocharges generated by the photoelectric conversion element, and a transfer gate configured to transmit the photocharges generated by the photoelectric conversion element to the floating diffusion region. The transfer gate includes a main transfer gate disposed to overlap a center section of the photoelectric conversion element and configured to operate in response to a first transmission signal, and a sub transfer gate disposed to overlap a boundary region of the photoelectric conversion element and configured to operate in response to a second potential level different from the first potential level.

Abstract: A light-emitting device includes a pair of light-transmissive insulator sheets disposed opposite to each other and two types of light-transmissive electroconductive layers disposed on a common one of or separately on one and the other of the pair of light-transmissive insulator sheets, and at least one light-emitting semiconductor each provided with a cathode and an anode which are individually and electrically connected to the two types of the light-transmissive electroconductive layers. The electrical connection and mechanical bonding between the members are improved by a light-transmissive elastomer which is between the pair of light-transmissive insulator sheets. A method in which a light-emitting semiconductor element and a light-transmissive electroconductive member are subjected to vacuum hot-pressing.

Abstract: An LED-filament comprising: a partially light transmissive substrate; a plurality of LED chips on a front face of the substrate; a photoluminescence material that is in direct contact with and covers all of the plurality of LED chips; and a light scattering layer that is in direct contact with and covers at least the photoluminescence material, wherein the light scattering layer comprises particles of light scattering material, and wherein the photoluminescence material comprises broadband green to red photoluminescence materials and narrowband red photoluminescence material.

Abstract: The light-emitting diode package includes a plurality of bumps being a couple corresponding to each other. Each of the bumps has a first part and a second part placed under the first part, and a gap is formed between the bumps in a period-repeating wriggle shape or an irregular wriggle shape. Accordingly, the distance between the bumps of the light-emitting diode package is small, which results in a less stress being concentrated at the space between the bumps, as a result, a crack is difficultly caused by the stress to the light-emitting diode package, in other words, the structural strength between the bumps and the covering part is enhanced. Still, while being manufactured, the yield rate of the light-emitting diode package is also improved since there is almost no crack to reduce the yield rate.

Abstract: A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion.

Abstract: A method for fabricating a hermetic electronic package includes providing a package body; hermetically coupling a package base plate to the package body; thermally coupling a substrate to the base plate; thermally mounting a semiconductor device to the substrate; bonding at least one high-current input/output (I/O) terminal to the first metalized region of the substrate by a strap terminal that is an integral high current heatsink terminal. A ceramic seal surrounding the at least one high-current I/O terminal is hermetically bonded to an outer surface of the package body. A metal hermetic seal washer surrounding the at least one high-current I/O terminal is hermetically bonded to the ceramic seal and to a portion of the at least one high-current I/O terminal. A lid is seam welded onto the package body.

Abstract: A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.

Abstract: Methods and apparatus for a cooling plate for solid state power amplifiers are provided herein. In some embodiments, a cooling plate of a solid state power amplifier includes a body having a rectangular shape, a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall; a plurality of holes disposed on a first side of the body configured to mount a plurality of heat generating microelectronic components; and a channel having a plurality of segments disposed within the body and extending from a first port disposed on the first sidewall to a second port disposed on the first sidewall.

Abstract: A semiconductor device according to an embodiment may include a plurality of light emitting structures, a first electrode disposed around the plurality of light emitting structures, a second electrode disposed on an upper surface of the plurality of light emitting structures, a first bonding pad electrically connected to the first electrode, and a second bonding pad electrically connected to the second electrode. The plurality of light emitting structures may include a first light emitting structure that includes a first DBR layer of a first conductivity type, a first active layer disposed on the first DBR layer, and a second DBR layer of a second conductivity type disposed on the first active layer; and a second light emitting structure that includes a third DBR layer of the first conductivity type, a second active layer disposed on the third DBR layer, and a fourth DBR layer of the second conductivity type disposed on the second active layer.

Abstract: A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.

Abstract: An optoelectronic component may include a semiconductor chip configured to emit radiation and a reflection element disposed in the beam path of the semiconductor chip where the reflection element is configured to reflect radiation. The reflection element may include a matrix material having diffuser particles and filler particles embedded therein. The diffuser particles are different from the filler particles. The filler particles may include a matrix having scatter particles embedded therein and/or a ceramic comprising the scatter particles in sintered form.

Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

Abstract: An image sensor and a method of fabricating the image sensor, the image sensor including a semiconductor substrate having a first floating diffusion region, a molding pattern over the first floating diffusion region and including an opening, a first photoelectric conversion part at a surface of the semiconductor substrate, and a first transfer transistor connecting the first photoelectric conversion part to the first floating diffusion region. The first transfer transistor includes a channel pattern in the opening and a first transfer gate electrode. The channel pattern includes an oxide semiconductor. The channel pattern also includes a sidewall portion that covers a side surface of the opening, and a center portion that extends from the sidewall portion to a region over the first transfer gate electrode.

Abstract: A display device comprises a substrate provided with a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, a first electrode provided on the substrate, an organic light emitting layer arranged on the first electrode, and a second electrode arranged on the organic light emitting layer, wherein the organic light emitting layer includes a first organic light emitting layer and a second organic light emitting layer, the first organic light emitting layer and the second organic light emitting layer are arranged on the first subpixel, the second subpixel, and the fourth subpixel, only the second organic light emitting layer is arranged on the third subpixel, only the first organic light emitting layer emits light on the first subpixel and the second subpixel, only the second organic light emitting layer emits light on the third subpixel, and both of the first organic light emitting layer and the second light emitting layer emit light on the fourth subpixel.

Abstract: An organic light emitting display device includes a substrate, a lower electrode, a light emitting layer, an upper electrode, and a light guide structure. The substrate includes a sub-pixel region and a transparent region. The lower electrode is disposed in the sub-pixel region on the substrate. The light emitting layer is disposed on the lower electrode, and includes an organic emission layer. The upper electrode is disposed on the light emitting layer. The light guide structure is disposed on the upper electrode, and partially overlaps the organic emission layer that is located at the sub-pixel region and the substrate that is located at the transparent region in a plan view.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: Image sensors include a pixel die that is stacked on a logic die. The logic die includes at least one function logic element disposed on a bond side thereof, and a logic oxide array of raised logic oxide features also disposed on the bond side. The pixel die includes a pixel array disposed on a light receiving side thereof, and a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. A plurality of outer bonds is disposed between an outer region of the logic die and an outer region of the pixel die. A plurality of inner bonds is formed at an inner region of the image sensor between the pixel oxide array and the logic oxide array, the inner bonds being spaced apart by a plurality of fluidly connected air gaps that extend between the logic die and the pixel die.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A display panel including an active area including organic light emitting elements therein; and an edge area adjacent to the active area and including a power line and auxiliary electrode therein, the auxiliary electrode being connected to the power line, and the edge area including margin and contact areas, wherein the organic light emitting elements include a first electrode; a second electrode on; and organic layers between the first electrode and the second electrode, wherein the auxiliary electrode and the second electrode are spaced apart from each other in the margin areas and are connected to each other in the contact areas, and wherein the contact areas and the margin areas face, and are spaced apart in a first direction from, the first electrodes that are adjacent to the edge area, and wherein the contact and margin areas are alternately arranged in a second direction that intersects the first direction.

Abstract: An LED-filament comprising: a partially light-transmissive substrate; a plurality of blue LED chips mounted on a front face of the substrate; first broad-band green to red photoluminescence materials and a first narrow-band manganese-activated fluoride red photoluminescence material covering the plurality of blue LED chips and the front face of the substrate; and second broad-band green to red photoluminescence materials covering the back face of the substrate. The LED-filament can further comprise a second narrow-band manganese-activated fluoride red photoluminescence material on the back face of the substrate in an amount that is less than 5 wt % of a total red photoluminescence material content on the back face of the substrate.