Patents Examined by David Chen
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Patent number: 11329196Abstract: A mounting structure for mounting a set of optoelectronic devices is provided. A mounting structure for a set of optoelectronic devices can include: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink can be located adjacent to the mounting structure. The set of optoelectronic devices can be mounted on a side of the mounting structure opposite of the heatsink.Type: GrantFiled: March 20, 2018Date of Patent: May 10, 2022Assignee: Sensor Electronic Technology, Inc.Inventors: Michael Shur, Grigory Simin, Alexander Dobrinsky
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Patent number: 11329062Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material.Type: GrantFiled: December 21, 2018Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Erik Byers, Merri L. Carlson, Indra V. Chary, Damir Fazil, John D. Hopkins, Nancy M. Lomeli, Eldon Nelson, Joel D. Peterson, Dimitrios Pavlopoulos, Paolo Tessariol, Lifang Xu
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Patent number: 11322533Abstract: There is provided a solid state image sensor including a photoelectric conversion unit formed and embedded in a semiconductor substrate, an impurity region that retains an electric charge generated by the photoelectric conversion unit, and a transfer transistor that transfers the electric charge to the impurity region. A gate electrode of the transfer transistor is formed in a depth direction toward the photoelectric conversion unit in the semiconductor substrate, from a surface of the semiconductor substrate on which the impurity region is formed. A channel portion of the transfer transistor is surrounded by the gate electrode in two or more directions other than a direction of the impurity region, as seen from the depth direction.Type: GrantFiled: February 28, 2014Date of Patent: May 3, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinya Yamakawa
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Patent number: 11251157Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.Type: GrantFiled: March 29, 2018Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Jung Yang, Hsien-Wei Chen
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Patent number: 11245033Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.Type: GrantFiled: July 30, 2018Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
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Patent number: 11245002Abstract: A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.Type: GrantFiled: December 21, 2018Date of Patent: February 8, 2022Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Rolf Weis, Henning Feick, Franz Hirler, Andreas Meiser
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Patent number: 11205669Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.Type: GrantFiled: May 27, 2015Date of Patent: December 21, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Okamoto, Yoshiyuki Kurokawa, Hiroki Inoue, Takuro Ohmaru
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Patent number: 11195929Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 ?. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.Type: GrantFiled: October 30, 2019Date of Patent: December 7, 2021Assignees: International Business Machines Corporation, ULVAC, INC.Inventors: Takashi Ando, Ruqiang Bao, Masanobu Hatanaka, Vijay Narayanan, Yohei Ogawa, John Rozen
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Patent number: 11192781Abstract: A semiconductor device includes: a silicon layer in which a trench is disposed; a surface structure portion disposed on the silicon layer at a position distant from the trench and having a surface provided by a metal layer; and a low electric conductivity portion disposed on the surface of the metal layer or in a part of the resist disposed on the trench side of the metal layer, and having an electric conductivity lower than at least a part of the metal layer covering a trench side portion of the surface of the metal layer.Type: GrantFiled: April 5, 2019Date of Patent: December 7, 2021Assignee: DENSO CORPORATIONInventors: Takahiro Higuchi, Yusuke Kawai, Sumio Ito
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Patent number: 11177299Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.Type: GrantFiled: May 27, 2015Date of Patent: November 16, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Okamoto, Yoshiyuki Kurokawa, Hiroki Inoue, Takuro Ohmaru
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Patent number: 11171177Abstract: A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.Type: GrantFiled: January 9, 2019Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Nathan A. Wilkerson, Mihir Bohra
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Package structure having sensor die with touch sensing electrode, and method of fabricating the same
Patent number: 11158555Abstract: A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.Type: GrantFiled: March 29, 2018Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Ting Kuo, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Chih-Hsuan Tai, Ying-Cheng Tseng -
Patent number: 11158725Abstract: The fin structure includes a first portion and a second, lower portion separated at a transition. The first portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.Type: GrantFiled: July 15, 2019Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Yuan, Hung-Ming Chen, Tsung-Lin Lee, Chang-Yun Chang, Clement Hsingjen Wann
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Patent number: 11152224Abstract: First and second n-type field stop layers in an n? drift region come into contact with a p+ collector layer. The first n-type field stop layer has an impurity concentration reduced toward an n+ emitter region at a steep gradient. The second n-type field stop layer has an impurity concentration distribution in which impurity concentration is reduced toward the n+ emitter region at a gentler gradient than that in the first n-type field stop layer and the impurity concentration of a peak position is less than that in the impurity concentration distribution of the first n-type field stop layer. The impurity concentration distributions of the first and second n-type field stop layers have the same peak position. The first and second n-type field stop layers are formed using annealing and first and second proton irradiation processes which have the same projected range and different acceleration energy levels.Type: GrantFiled: March 15, 2013Date of Patent: October 19, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tomonori Mizushima
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Patent number: 11133334Abstract: An array substrate, a manufacturing method thereof, and a display device including the array substrate. The array substrate includes a plurality of gate line groups and a plurality of data lines disposed on a substrate, the plurality of gate line groups intersecting with the plurality of data lines to define a plurality of pixel units arranged in an array, wherein each of the plurality of gate line groups includes a first gate line and a second gate line insulated from each other, and orthographic projections of the first gate line and the second gate line of each of the plurality of gate line groups on the substrate at least partially overlap.Type: GrantFiled: May 21, 2018Date of Patent: September 28, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xiang Wang, Zhen Zhang, Ru Zhou
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Patent number: 11127868Abstract: A photon-activated quantum dot capacitor and method of fabrication. A photon-activated quantum dot capacitor photodetector having a read only integrated circuit; and a photon-activated quantum dot capacitor chip hybridized with the read only integrated circuit, wherein said photon-activated quantum dot capacitor chip comprises colloidal quantum dots that detect photons as a change in a dielectric constant of the colloidal quantum dots of the photon-activated quantum dot capacitor chip, including the further implementation of a photodetector.Type: GrantFiled: October 31, 2017Date of Patent: September 21, 2021Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Pierre-Alain S. Auroux, Louise C. Sengupta, John E. King, Idan Mandelbaum, James A. Stobie, Laura A. Swafford, Chen J. Zhang, Christopher S. Badorrek, Michael J. Bowers, II, Myeongseob Kim, Tadd C. Kippeny, Don A. Harris
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Patent number: 11107848Abstract: The semiconductor device for detection of radiation comprises a semiconductor substrate (1) with a main surface (11), a dielectric layer (6) comprising at least one compound of a semiconductor material, an integrated circuit (2) including at least one component sensitive to radiation (3), a wiring (4) of the integrated circuit embedded in an intermetal layer (8) of the dielectric layer (6), an electrically conductive through-substrate via (5) contacting the wiring, and an optical filter element (7) arranged immediately on the dielectric layer above the component sensitive to radiation. The dielectric layer comprises a passivation layer (9) at least above the through-substrate via, the passivation layer comprises a dielectric material that is different from the intermetal layer (8), and the wiring is arranged between the main surface and the passivation layer.Type: GrantFiled: February 24, 2014Date of Patent: August 31, 2021Assignee: AMS AGInventors: Hubert Enichlmair, Franz Schrank, Joerg Siegert
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Patent number: 11075225Abstract: A display device including: a substrate including a display area for displaying an image and a non-display area positioned at a periphery of the display area; a plurality of pixels positioned at the display area; a plurality of data lines connected with the plurality of pixels; and a crack detecting line positioned at the non-display area, wherein the crack detecting line includes: a plurality of unit connectors extending in a first direction, wherein the first direction is parallel to an extending direction of a side of the substrate nearest to the unit connectors; and a plurality of wiring portion units connected to each other through the plurality of unit connectors, wherein the number of wiring portion units is an even number.Type: GrantFiled: April 12, 2018Date of Patent: July 27, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hey Jin Shin, Won Kyu Kwak, Seung-Kyu Lee
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Patent number: 11069688Abstract: Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing a bulk substrate with a first doped layer thereon, depositing a first hard mask over the substrate, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, where the grown second polysilicon material and epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material.Type: GrantFiled: May 22, 2018Date of Patent: July 20, 2021Assignee: International Business Machines CorporationInventor: Alexander Reznicek
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Patent number: 11063177Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.Type: GrantFiled: December 20, 2013Date of Patent: July 13, 2021Assignees: ALEDIA, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Eric Pourquier, Hubert Bono