Abstract: A method of playing a variation of Texas Hold'em poker in which each player is dealt three hole cards instead of the usual two. A player sets his three cards into two Texas Hold'em type hands, each having two cards, by selecting from among the three cards one card that is shared with each of the other two cards to form a two-card hand. Except for each player playing two hands, the rules of play are those of a traditional Texas Hold'em game with flop, turn and river board cards, and betting rounds after display of the flop, turn and river board cards. In two variations of the game, the players select their shared cards either prior to or after display of the board flop cards. Also, the shared cards can be opened either at the time they are selected or after the round of betting that follows display of the river card.

Abstract: A method for placing a component on a target platform includes providing component alignment marks, target platform reference marks, a first multiple-sensor probe including first sensors, and a second multiple-sensor probe including third sensors. The method further includes determining second sensors included in the first sensors, and sensing a first signal from a first one of the alignment marks by at least one of the second sensors. The method further includes determining fourth sensors included in the third sensors. The method further includes sensing a second signal from a second one of the alignment marks by at least one of the fourth sensors, and detecting a deviation of the component from the target platform associated with a first position of one of the second sensors that sense the first signal and a second position of one of the fourth sensors that sense the second signal.

Abstract: A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.

Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.

Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.

Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.

Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.

Abstract: A tool for forming a trench and a plurality of cooling holes within the trench includes a body, the body including a ridge portion extending along a first side of the tool. The ridge portion is operable to mate with a workpiece to form a trench on the workpiece. A plurality of electrodes extend from the ridge portion and are oriented to form a plurality of cooling holes within the trench on the workpiece.

Abstract: There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.

Abstract: There is provided a semiconductor package, and more particularly, a semiconductor package including an antenna embedded in an inner portion thereof. The semiconductor package includes: a semiconductor chip; a main antenna disposed to be adjacent to the semiconductor chip and electrically connected thereto; a sealing part sealing both of the semiconductor chip and the main antenna; and an auxiliary antenna formed on an outer surface of the sealing part and coupled to the main antenna.

Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 ?m, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a?) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

Abstract: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: The disclosure provides a manufacturing method for an LED package. A first luminescent conversion layer comprising one first luminescent conversion element is located on an LED chip, wherein the first luminescent conversion element is precipitated via centrifugation around the LED chip without sheltering the LED chip. Thereafter, a second luminescent conversion layer is located on the first luminescent conversion layer. The second luminescent layer has a second luminescent conversion element which has an excited efficiency lower that that of the first luminescent conversion element.

Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a first radiator member arranged on and thermally coupled to the semiconductor element, and a second radiator member arranged on and thermally coupled to the first radiator member. The second radiator member includes projections which project out toward the first radiator member. The projections are formed on a circumference of a concentric circle with respect to a center point of the second radiator member. The first radiator member includes grooves in which the projections are movable. The grooves are formed on a circumference of a concentric circle with respect to a center point of the first radiator member. The projections are fitted to terminating ends of the grooves with the center point of the first radiator member and the center point of the second radiator member coincided.

Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, an apparatus for substrate processing includes a process chamber having a chamber body defining an inner volume; and a silicon containing coating disposed on an interior surface of the chamber body, wherein an outer surface of the silicon containing coating is at least 35 percent silicon (Si) by atom. In some embodiments, a method for forming a silicon containing coating in a process chamber includes providing a first process gas comprising a silicon containing gas to an inner volume of the process chamber; and forming a silicon containing coating on an interior surface of the process chamber, wherein an outer surface of the silicon containing coating is at least 35 percent silicon.

Abstract: A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced.