Abstract: There is provided a resin dispensing apparatus for a light emitting device package and a method of manufacturing a light emitting device package using the same. The resin dispensing apparatus includes a resin dispensing part including a resin storage portion filled with a resin therein and a resin discharge portion combined with the resin storage portion and discharging the resin therefrom; a supporting part having a light emitting device package disposed on an upper surface thereof and electrically connected to the light emitting device package; a voltage applying part having both terminals respectively connected to the resin dispensing part and the supporting part to apply a voltage thereto; and a sensing part electrically connected to the resin dispensing part and the supporting part individually and sensing a contact between the resin dispensing part and the light emitting device package with an electrical signal.

Abstract: A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Abstract: The present invention relates to a light emitting diode (LED) lamp, and an object of the present invention is to provide an LED lamp in which an LED can be easily exchanged and external vibration can be absorbed to prevent the play thereof. To this end, an LED lamp according to the present invention comprises an LED package having a lead frame; a printed circuit board separated from the LED package and having a conductive pattern formed on a surface thereof facing the lead frame; and a pressing means for pressing the LED package toward the PCB so that the lead frame is in contact with the conductive pattern.

Abstract: A fabric cutting system and/or method can include a mandrel having a body and first and second legs, a centered chuck, and an offset chuck, each chuck configured to receive either one of the legs or body to rotatingly support the mandrel between the chucks. When one of the legs is inserted into the centered chuck and the mandrel body is inserted into the offset chuck, the mandrel can be rotated and the fabric mounted on the mandrel can be cut about the leg at a location beyond the end of the other leg. One of the legs can include a leg extension removable from a leg base that when removed allows the other leg to be cut beyond the end of the leg base. The fabric can be cut with a cutting laser, which may be a multi-axis laser, and/or have low power.

Abstract: Disclosed is a white LED device using a multi-package. The white LED device maximizes the efficiency of a green LED in the yellow gap to minimize a deviation in performance between the other color chips, in comparison with conventional white LED devices using RGB multi-chips. In addition, deviations in temperature, current and droop characteristics between the chips can be minimized, contributing to the simplification of a driving circuit. Therefore, the white LED device is suitable for commercialization. Furthermore, the white LED device has a higher color rendering index (Ra) (>80) than conventional white LED devices having single-package structures. The correlated color temperatures of the white LED device are controllable in the range of 2,700 to 12,000 K. The white LED device can express abundant colors for emotion lighting and can emit white light with high efficiency.

Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.

Abstract: The present invention is a system for conducting a combat simulation game in which each player is outfitted with equipment enabling data concerning the game play ability of the player to be transmitted to a local server for use in computing a player performance data for individual players in comparison with all other players having data stored within the system. The equipment transmits various data to the server which is utilized by the server to update the player performance data in a real-time manner that can be accessed and viewed by other players from remote locations.

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: A forming 7 die is filled with a powder (11) of electrode material, the powder (11) of electrode material filled in the forming die is compressed to form a porous powder compact (27), the porous powder compact (27) is set in place in a chamber (25) of a heat-treating furnace (23), the chamber (25) is supplied with inert gas or hydrogen gas, and inert gas or hydrogen gas is heated by heaters (39) in the heat-treating furnace (23) and blown toward the powder compact (27), as blows circulating in the chamber (25), whereby the powder compact is heated with heat of convection flows of inert gas or hydrogen gas, or mixed gas containing inert gas as principal component and hydrogen gas, so the electrode material of the powder compact is sintered.

Abstract: Embodiments of the present disclosure provide an apparatus that comprises a connection circuit situated within a substrate and configured to communicatively couple a first integrated circuit disposed adjacent to a top surface of the apparatus to a second integrated circuit disposed adjacent to a bottom surface of the apparatus. The apparatus further comprises one or more enclosed heat dissipation structures situated within the substrate and configured to convey heat away from the first and second integrated circuits.

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

Abstract: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.

Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract: Fabrication of a photonic integrated circuit (PIC) including active elements such as a semiconductor optical amplifier (SOA) and passive elements such as a floating rib waveguide. Selective area doping through ion implantation or thermal diffusion before semiconductor epitaxial growth is used in order to define the contact and lateral current transport layers for each active device, while leaving areas corresponding to the passive devices undoped. InP wafers are used as the substrate which may be selectively doped with silicon.

Abstract: An encapsulation structure including at least one hermetically sealed cavity in which a device, an electronic component produced on a first substrate, and a getter material layer covering the electronic component in order to block the gases capable of being degassed by the electronic component, are enclosed. A top surface of the device is free of contact with the getter material layer.

Abstract: A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature.

Abstract: A solar module includes a solar cell, a heat spreader layer disposed above the solar cell, and a cell interconnect disposed above the solar cell. From a top-down perspective, the heat spreader layer at least partially surrounds an exposed portion of the cell interconnect.