Patents Examined by David E. Graybill
  • Semiconductor package and mobile device using the same
    Patent number: 9721905
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
  • Pixel structure, array substrate and display device
    Patent number: 9704885
    Abstract: A pixel structure, an array substrate and a display device. The pixel substrate comprises a first pixel electrode and a second pixel electrode arranged in a first direction, and a thin film transistor (TFT) disposed between the first pixel electrode and the second pixel electrode. The TFT includes a comb-shaped source, a comb-shaped first drain and a comb-shaped second drain; and a channel region of the TFT is defined by the comb-shaped source respectively and the comb-shaped first drain and the comb-shaped second drain. The channel region has a greater ratio of width to length, thus improving the driving capability of the TFT for driving the first pixel electrode and the second pixel electrode.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: July 11, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Pan Li, Wenbo Li, Yong Qiao, Hongfei Cheng, Jianbo Xian
  • Liquid crystal display panel, array substrate and manufacturing method for thin-film transistor
    Patent number: 9698175
    Abstract: An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: July 4, 2017
    Assignee: Shenzhen China Star Optoelectionics Technology Co., Ltd
    Inventor: Dongzi Gao
  • Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same
    Patent number: 9691684
    Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hwa Park, Sung-hee Kang, Kwang-jin Moon, Byung-lyul Park, Suk-chul Bang
  • Methods for forming fan-out package structure
    Patent number: 9691726
    Abstract: A method includes forming a first composite wafer including molding a plurality of device dies and a plurality of through-vias in a first molding material, and forming redistribution lines on opposite sides of the first molding material. The redistribution lines are inter-coupled through the plurality of through-vias. The method further includes forming a second composite wafer including stacking a plurality of dies to form a plurality of die stacks, and molding the plurality of die stacks in a second molding material. The second molding material fills gaps between the plurality of die stacks. The first composite wafer is bonded to the second composite wafer to form a third composite wafer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsien-Wei Chen, Cheng-Lin Huang, Meng-Tse Chen, Chung-Shi Liu
  • Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same
    Patent number: 9679896
    Abstract: A moisture blocking structure includes an active fin disposed on a sealing region of a substrate, the substrate including a chip region and the sealing region surrounding a periphery of the chip region, the active fin continuously surrounding the chip region and having a winding line shape in a plan view. A gate structure covers the active fin and surrounds the periphery of the chip region. A conductive structure is disposed on the gate structure, the conductive structure surrounding the periphery of the chip region.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 13, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Soo Yoon, Min-Kwon Choi, Yang-Soo Son, Hyun-Jo Kim, Han-Ii Yu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9673149
    Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 6, 2017
    Assignees: Hannstar Display (Nanjing) Corporation, Hannstar Display Corporation
    Inventors: Chien-Hao Wu, Yi-Ting Lee
  • Method of manufacturing semiconductor device
    Patent number: 9660046
    Abstract: A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 23, 2017
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Sachiko Aoi, Yukihiko Watanabe, Katsumi Suzuki, Shoji Mizuno
  • Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
    Patent number: 9660159
    Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 23, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Keiji Sato, Shunpei Yamazaki
  • Method of inspecting by-products and method of manufacturing semiconductor device using the same
    Patent number: 9660186
    Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhye Bae, Wonjun Lee, Yoonsung Han, Hoon Han, Kyu-Man Hwang, Yongsun Ko
  • Packaged microelectronic elements having blind vias for heat dissipation
    Patent number: 9620433
    Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: April 11, 2017
    Assignee: Tessera, Inc.
    Inventor: David Edward Fisch
  • Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device
    Patent number: 9613816
    Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Chieh Tsai, Tz-Wei Lin, Sheng-Jen Yang, Hung-Yin Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
  • Mixed orientation semiconductor device and method
    Patent number: 9607986
    Abstract: A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jiang Yan, Danny Pak-Chum Shum, Armin Tilke
  • Fin isolation on a bulk wafer
    Patent number: 9601386
    Abstract: A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices. and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang
  • “L” shaped lead integrated circuit package
    Patent number: 9601417
    Abstract: Various aspects provide for bending a bending a lead frame of a semiconductor device package into a shape of an “L” and mounting the package on a substrate. A horizontal portion of the bent lead-frame is about parallel with a surface of the package. A vertical portion of the bent lead frame is configured to extend the horizontal portion beyond the surface of the package. A device may be mounted between the substrate and the package.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 21, 2017
    Assignee: Unigen Corporation
    Inventors: Hanjoo Na, Santosh Kumar
  • Graphene base transistor and method for making the same
    Patent number: 9590045
    Abstract: A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 7, 2017
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ—INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Andre Wolff, Wolfgang Mehr, Grzegorz Lupina, Jaroslaw Dabrowski, Gunther Lippert, Mindaugas Lukosius, Chafik Meliani, Christian Wenger
  • Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element
    Patent number: 9583498
    Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package
    Patent number: 9570429
    Abstract: The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 14, 2017
    Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianhong Mao, Fengqin Han, Zhiwei Wang, Wenfen Chang
  • Flexible display device
    Patent number: 9564079
    Abstract: A flexible display device includes a flexible display panel including: a plastic film; a pixel circuit on the plastic film; a light emitting element; and an inorganic layer. Openings are in the inorganic layer along a cutting line for cutting the flexible display panel.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: February 7, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jun Namkung
  • Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element
    Patent number: 9559107
    Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 31, 2017
    Assignee: International Businesss Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo