Abstract: An electronic control unit (ECU) is disposed in a vehicle, and includes an input section and a controller. The input section inputs vehicle data from vehicle sensors and actuator to the controller. The controller includes a priority setter and a transmission data generator. The transmission data generator transmits transmission object data, which is data for transmission to an external device and generated from the vehicle data. The priority setter sets priority of the transmission object data based on priority setting data, which is data included in the vehicle data. The transmission data generator performs an adjustment process for adjusting an amount of transmission data based on the priority. The ECU provides an efficient transmission of data by limiting and/or preventing an increase in the amount of transmission data.

Abstract: Systems and techniques for synchronizing transactions between processing devices on an interconnection network are provided. Upon receiving a stream of posted transactions followed by a flush transaction from a source processing device connected to the interconnection network, the flush transaction is trapped before it enters the interconnecting network. Subsequently, based on monitoring for responses received from a destination processing device for transactions corresponding to the posted transactions, a flush response is generated and returned to the source processing device. The described techniques enable efficient synchronizing posted writes, posted atomics and the like over complex interconnection fabrics such that a first GPU can write data to a second GPU so that a third GPU can safely consume the data written to the second GPU.

Abstract: The present application is directed to adding a CEC engine into a CEC HDMI Switch used to provide universal remote-control capabilities even on TVs that do not support the CEC protocol.

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.

Abstract: A method for increasing effective storage capacity in a heterogeneous storage array is disclosed. In one embodiment, such a method determines a number of smaller-capacity storage drives and a number of larger-capacity storage drives in a storage array. The method further determines which RAID arrays in the storage array may be composed exclusively of the larger-capacity storage drives. Using this information, the method establishes a first set of RAID arrays in the storage array that will be composed exclusively of the larger-capacity storage drives and a second set of RAID arrays that may contain the smaller-capacity storage drives. The method then initiates a process to swap the smaller-capacity storage drives in the first set with the larger-capacity storage drives in the second set until the first set of RAID arrays is composed exclusively of the larger-capacity storage drives. A corresponding system and computer program product are also disclosed.

Abstract: A system includes storage, in a volatile random access memory, of a first data block comprising an array of distinct values of a database table column, and first header data comprising a first pointer to the first data block, determination of a memory size associated with the first header data and the first data block, allocation of a first memory block of the non-volatile random access memory based on the determined memory size, determination of an address of the non-volatile random access memory associated with the allocated first memory block, and writing of an indicator of the number of distinct values of the array and a binary copy of the first data block at the address of the non-volatile random access memory.

Abstract: Exemplary methods, apparatuses, and systems include receiving an instruction to atomically write data to a memory component. A plurality of write commands for the first data are generated, including an end of atom indicator. The first plurality of write commands are sent to the memory component while accumulating a plurality of translation table updates corresponding to the write commands One or more translation tables are updated with the plurality of translation table updates in response to determining that the final write command has been successfully sent to the memory component.

Abstract: A system in which first header data and a first logical array are stored in a volatile random access memory, the first logical array stored in a first contiguous memory block, with each array position of the first logical array representing a position in a database table and storing a value identifier of a value associated with the position in the database table, and with the first header data indicating a number of bits used to encode the value identifiers and comprising a first pointer to the first contiguous memory block. A memory size associated with the first header data and the first contiguous memory block is determined, a first memory block of the non-volatile random access memory is allocated based on the determined memory size, an address of the non-volatile random access memory associated with the allocated first memory block is determined, and the number of bits and a binary copy of the first contiguous memory block are written at the address of the non-volatile random access memory.

Abstract: Aspects for vector circular shifting in neural network are described herein. The aspects may include a direct memory access unit configured to receive a vector that includes multiple elements. The multiple elements are stored in a one-dimensional data structure. The direct memory access unit may store the vector in a vector caching unit. The aspects may further include an instruction caching unit configured to receive a vector shifting instruction that includes a step length for shifting the elements in the vector. Further still, the aspects may include a computation module configured to shift the elements of the vector toward one direction by the step length.

Abstract: A noise detection device includes a drive circuit, a sense circuit and a controller. The drive circuit drives a plurality of drive lines having a first polarity pattern and a second polarity pattern, wherein an operation of the first polarity pattern and the second polarity pattern substantially equals zero over a predetermined time period. The sense circuit senses a plurality of sense signals from at least one sense line during the predetermined time period. The controller derives a magnitude of a noise signal from the at least one sense line according to the sense signals.

Abstract: A data storage system for managing storage of data from clients includes a data storage and a data storage orchestrator. The data storage includes an accelerator pool and a non-accelerator pool. The data storage orchestrator identifies a client assignment update event based on a change in use of the data storage by a client of the clients, makes a determination that the client assignment update event is a promotion event, and in response to the determination: promotes the client to move a primary data storage of the client from the non-accelerator pool to the accelerator pool.

Abstract: The present disclosure provides a cable modem and an operating method thereof. This method includes steps as follows. After receiving a boot command, it is checked whether a boot data of a main storage area of a flash memory is complete. When the boot data of the main storage area of the flash memory is not complete, a backup data is copied from a backup storage area to overwrite the boot data of the main storage area. Then, the boot data in the main storage area is used to continue the boot process.

Abstract: In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.

Abstract: A data processing system and a method of runtime configuration of the data processing system are disclosed. The data processing system comprises a plurality of home nodes, and for a data store associated with a slave node in the data processing system, for each home node of the plurality of home nodes a modified size of the data store is determined. The modified size is based on a storage capacity of the data store and at least one additional property of the data processing system. A chosen home node of the plurality of home nodes is selected which satisfies a minimization criterion for the modified size, and the chosen home node is paired with the slave node.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a motherboard, a plurality of information handling resources communicatively coupled to the motherboard, a socket communicatively coupled to the motherboard and configured to receive one of a plurality of different types of interposers, wherein each of the plurality of interposers is configured to provide routing of electrical signals between the socket and a respective system on a chip communicatively coupled to such interposer, and a configuration module. The configuration module may be configured to receive identifying information associated with an interposer, of the plurality of interposers, communicatively coupled to the socket and based on the identifying information, configure the plurality of information handling resources for interoperability with a system on a chip communicatively coupled to the interposer.

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

Abstract: The disclosure provides for a reactive cache coherence protocol that has efficiencies over proactive approaches. Rather than proactively performing remediation when a data item is invalidated, a destination endpoint checks cache coherence upon receiving an indication of a cache hit, and based at least on detecting a lack of coherence, performs a reactive remediation process. For example, the incoherence may be fixed by replacing, as a cached data item, a data block indicated by the cache hit with a replacement data block that triggered the cache hit.

Abstract: A peripheral processing device comprises a physical interface for connecting the processing device to a host computing device through a communications protocol. A local controller connected to local memory across an internal bus provides input/output access to data stored on the processing device to the host through a file system API. A neural processor comprises at least one network processing engine for processing a layer of a neural network according to a network configuration. A memory at least temporarily stores network configuration information, input image information, intermediate image information and output information produced by each network processing engine. The local controller is arranged to receive network configuration information through a file system API write command, to receive input image information through a file system API write command; and to write output information to the local memory for retrieval by the host through a file system API read command.

Abstract: To start power supply at a high current without applying USB Power Delivery, a power supply system includes a power supply device having a first USB connector conforming to the USB Type-C standard, and a power receiving device having a second USB connector conforming to the USB Type-C standard. The second USB connector includes a high current notification pin for notifying that it is possible to receive power at a high current greater than a predetermined reference current. When the second USB connector is coupled to the first USB connector, the power receiving device notifies the power supply device of the fact that it is possible to receive power at a high current greater than the predetermined reference current, through the high current notification pin. When receiving the notification, the power supply device determines that it is possible to start power supply to the receiving device at a high current.