Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.

Abstract: A method for increasing compatibility of DisplayPort includes: providing a first source device, a second source device, a controller, and a sink device, wherein the first source device is connected to the controller; the first source device transmitting a first image signal to the sink device via a main link for displaying the first image signal on the sink device; causing the controller to disconnect from the first source device and connect to the second source device; executing a simulation process to generate a DC level variation on an auxiliary channel between the controller and the sink device; the second source device transmitting auxiliary data to the sink device; the sink device transmitting link data back to the second source device; and the second source device transmitting a second image signal to the sink device via a second main link for displaying the second image signal on the sink device.

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

Abstract: Present disclosure relates to a method for managing a docking device and the docking device thereof. The docking device is configured with a processor and at least two coupling ports. The method comprises following steps: electrically coupling a computer and/or at least one peripheral device to the at least two coupling ports respectively; retrieving a plurality of characteristic profiles by the processor, wherein each of the characteristic profiles is retrieved from each of the at least two coupling ports; receiving, by the processor, an input signal from the computer or the at least one peripheral device; and changing the characteristic profiles based on the input signal by the processor.

Abstract: A solution to the technical problem of improving device-to-device connection speeds includes the use of single-wire communication (SWC). Unlike the two differential wires required in transmission lines, SWC includes a transmission method using a single wire for data without requiring a return wire. The use of SWC has the potential to enable low loss channels of increasingly high bandwidth. The SWC improvements in bandwidth and frequency enable a significant reduction of power required for communication. SWC provides significant improvement in speed for each channel, so fewer wires may be used for each device-to-device connection. SWC also provides the ability to convey increased bandwidth and increased power over each wire, which further reduces the number of wires needed to provide power and communication.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: Embodiments for managing High-Definition Multimedia Interface (HDMI) data, such as an HDMI device, are provided. The HDMI device includes a body, first and second HDMI connectors coupled to the body, and an electronic assembly coupled to the body. The electronic assembly is configured to operate in a first mode and a second mode. In the first mode of operation, the electronic assembly causes HDMI data received at the second HDMI connector to be transmitted to the first HDMI connector. In the second mode of operation, the electronic assembly does not cause the HDMI data received at the second HDMI connector to be transmitted to the first HDMI connector.

Abstract: A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.

Abstract: Command list processing in performing parallel IO operations is disclosed. In one example, handling IO requests directed to an operating system having an IO scheduling component entails allocating a command to a thread in association with an IO request. The command is allocated from one of a plurality of command lists accessible in parallel, and the command is also linked to one of a plurality of active command lists that are accessible in parallel. The command lists can be arranged as per-CPU command lists, with each per-CPU command list corresponding to one of a plurality of CPUs on a multi-core processing platform on which the IO requests are processed. Similarly, each of the active command lists can respectively correspond to one of the plurality of CPUs on the multi-core processing platform. Per-volume queues can also be implemented for respective volumes presented to applications.

Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and/or the determined access to the second device.

Abstract: An apparatus includes a first device connector configured to be coupled to a first device. The apparatus also includes a second device connector configured to be coupled to a second device. The apparatus further includes at least two connection arms forming a hinged connection between the first device connector and the second device connector. In addition, the apparatus includes a flexible connector coupled to the first device connector and the second device connector, at least a portion of the flexible connector extending through the at least two connection arms, the flexible connector comprising a flexible printed circuit board assembly (PCBA) or a flexible flat cable (FFC).

Abstract: An audio/video (A/V) hub that determines an environment of a portable electronic device is described. In particular, the A/V hub may identify the environment based on performance information about communication between the portable electronic device and receiver devices (which was received from the receiver devices), and a history of behavior of an individual associated with the portable electronic device and the A/V hub. Alternatively, the A/V hub may identify the environment based on performance information about communication between the portable electronic device and the A/V hub and the portable electronic device and another A/V hub (which was received from the portable electronic device and/or the other A/V hub), and a history of behavior of an individual associated with the portable electronic device and the A/V hub. Based on the determination, the A/V hub provides an instruction to power on an A/V display device in the environment.

Abstract: A system and method are described for configuring a motherboard using expansion cards plugged into motherboard slots. In particular, each of the expansion cards can include a control signal that is supplied to the motherboard and that can configure hardware positioned on the motherboard. In one embodiment, the configuration allows a communication path to be switched on to allow the expansion cards to cross communicate.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

Abstract: An application execution method for improving the operation speed of the application in executing or in the middle of running the application is provided. The application execution method includes detecting a launch of an application, preloading Input/Outputs (I/Os) requested at the launch based on profile data with I/Os requested at a previous launch of the application, and updating the profile data based on at least one of the I/Os requested at current and previous launches of the application.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.