Abstract: A data transmission system includes a first apparatus that is connected to a first external apparatus using the first transmission scheme and a second apparatus that is connected to a second external apparatus using the first transmission scheme. The first apparatus is connected to the second apparatus using a second transmission scheme that is different from the first transmission scheme. When the operation mode of the first apparatus in the first transmission scheme and the operation mode of the second apparatus in the first transmission scheme are different, data in the first external apparatus or the second external apparatus is transmitted to the second external apparatus or the first external apparatus, respectively, via the first apparatus and the second apparatus.

Abstract: The USB chipset including a data processing unit, a transmitting unit, a first pin set and a second pin set is provided. The data processing unit generates a plurality of transmission information according to first information provided by a first device. The transmitting unit processes the transmission information to generate an output signal. The first pin set is configured to transmit the output signal to a second device. The second pin set is configured to transmit the output signal to the second device. When the first pin set transmits the output signal to the second device, the second pin set does not transmit the output signal to the second device. When the second pin set transmits the output signal to the second device, the first pin set does not transmit the output signal to the second device.

Abstract: Command list processing in performing parallel IO operations is disclosed. In one example, handling IO requests directed to an operating system having an IO scheduling component entails allocating a command to a thread in association with an IO request. The command is allocated from one of a plurality of command lists accessible in parallel, and the command is also linked to one of a plurality of active command lists that are accessible in parallel. The command lists can be arranged as per-CPU command lists, with each per-CPU command list corresponding to one of a plurality of CPUs on a multi-core processing platform on which the IO requests are processed. Similarly, each of the active command lists can respectively correspond to one of the plurality of CPUs on the multi-core processing platform. Per-volume queues can also be implemented for respective volumes presented to applications.

Abstract: According to the present invention, congestion in a network band is suppressed. This information processing apparatus is provided with: a command reception unit that receives commands from at least one application given to at least two device groups; a device specification unit that specifies devices belonging to the at least two device groups when the commands from the at least one application given to the at least two device groups are of a similar type; and a command transmission control unit that executes control transmission so as to prevent overlap of transmission of the commands to the specified devices.

Abstract: The invention relates to an apparatus, a device and a method. The apparatus is configured for providing an address to a device attachable with the apparatus. The apparatus comprises at least one connector capable of receiving the device, an address composer for producing an address signal, and an address line in the connector for providing the address signal to the device, the address signal being indicative of an address to be used by the device when attached with the apparatus. The address composer is configured to generate the address signal as an analogue address signal.

Abstract: A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.

Abstract: A method for accessing a peripheral device via a wide area communication network. A control device receives a data item indicating that the peripheral device is connected via a series interface to an access device having access to the wide area communication network. The control device sends to the home device a command for its association with the peripheral device using an address associated with the access device. The home device then sends a command for the transfer of the peripheral device resources to the access device. This association enables the home device to access the peripheral device remotely in order to use the latter via a driver for the peripheral device installed on the home device.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Systems and methods are provided that allow a secure processing system (SPS) to be implemented as a hard macro, thereby isolating the SPS from a peripheral processing system (PPS). The SPS and the PPS, combination, may form a secure element that can be used in conjunction with a host device and a connectivity device to allow the host device to engage in secure transactions, such as mobile payment over a near field communications (NFC) connection. As a result of the SPS being implemented as a hard macro isolated from the PPS, the SPS may be certified once, and re-used in other host devices without necessitating re-certification.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operational state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward data it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Apparatus and method relate to a data channel. In this apparatus, an input circuit is configured to gate a valid input with a ready output to provide a forward token (“f-token”) to a first f-token register of a f-token pipeline and to a counter, and to receive data to a first data register of a data pipeline. An output circuit is configured to gate a ready input with a valid output to provide a return token (“r-token”) to a first r-token register of a r-token pipeline and to a FWFT FIFO, to receive the f-token from a second f-token register of the f-token pipeline to the FWFT FIFO, and to receive the data from a second data register of the data pipeline to the FWFT FIFO. The input circuit receives the r-token from the first r-token register to a second r-token register of the r-token pipeline for the counter.

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: Systems and methods for asynchronous mapping of a hot-plugged I/O device associated with a virtual machine. An example method comprises: executing, by a host computer system, a virtual machine managed by a hypervisor; responsive to detecting hot-plugging of an input/output (I/O) device, pinning a memory buffer associated with the I/O device; and responsive to receiving a signal indicating completion of pinning the memory buffer, notifying the virtual machine of the I/O device being hot-plugged.

Abstract: A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialization signal comprising port initialization data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialization signal comprising the port initialization data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialization signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialization data and the just obtained original one or more parity bits.

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: Elevator safety and safety related information needs to be sent reliably to safety controlling systems. Existing elevator communication devices may be used for transmitting this information by processing the received safety and safety related information and processing it before sending it over the communication bus from the elevator car or floor equipment to the controlling devices. A separate communication unit may be used for receiving and processing safety and safety related data packets before they are transmitted over a common bus used for safety and safety non-critical submission.

Abstract: An electronic unit for a vehicle communication interface, and a vehicle communication interface of that kind, are described. The electronic unit includes a switch matrix having at least one low-leakage-current switch that is designed to interrupt both communication devices simultaneously.