Patents Examined by David E. Martinez
  • Methods and apparatus for management of data connections to a peripheral device
    Patent number: 10713184
    Abstract: Interface circuitry is provided for a host device, the interface circuitry for controlling data connections between the host device and a peripheral device.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Robert David Rand, Bradley Allan Lambert
  • Memory module threading with staggered data transfers
    Patent number: 10705988
    Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Frederick A Ware
  • Data bit width converter and system on chip thereof
    Patent number: 10698851
    Abstract: A data bit width converter is adapted to: convert first data using a first bit width as a data segment unit and second data using a second bit width as a data segment unit, and provide a cache to temporarily store third data, wherein the first bit width is not equal to the second bit width. The data bit width converter includes a slave, a cache, and a data reconstitution circuit. The slave is configured to read and write the second data. The cache is configured to read and write the third data. The data reconstitution circuit is configured to: convert the first data and the second data, and sequentially search the cache and the slave for the second data according to a searching program, to output the first data, and write the third data to the cache according to a temporary storage program.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 30, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Kai-Ting Shr, Chia-Wei Yu
  • System and interface circuit for driving data transmission line to termination voltage
    Patent number: 10698848
    Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Hae Kang Jung
  • Universal flash storage, electronic device capable of connecting to a plurality type of memory devices and method thereof
    Patent number: 10691624
    Abstract: An electronic device including a connector and a method therefor are provided. The electronic device includes a connector for mounting at least one of a universal flash storage (UFS) card, a secure digital (SD) card, or a universal integrated circuit card (UICC). The connector includes a first power terminal for connecting the SD card or the UFS card, a second power terminal for connecting the UFS card or the UICC, and one or more signal terminals for connecting at least one of the UFS card, the SD card, and the UICC, and a processor configured to detect a card mounted in the connector, output to the UFS card a first designated voltage and a second designated voltage, and reset the UFS card through the one or more signal terminals, or output the first designated voltage and a third designated voltage, and reset a corresponding SD card or the UICC.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghui Sunwoo, Jungsik Park
  • Method and system for high-density converged storage via memory bus
    Patent number: 10678443
    Abstract: One embodiment facilitates a high-density converged storage system. During operation, the system receives, by a volatile memory of a storage device via a memory bus, data to be stored in a non-volatile memory of the same storage device. The system writes, by a controller of the storage device, the data directly to the non-volatile memory via the volatile memory, e.g., without using a serial bus protocol.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: June 9, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Shu Li, Jianjian Huo
  • Apparatus for connecting non-volatile memory locally to a GPU through a local switch
    Patent number: 10678733
    Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 9, 2020
    Assignee: ATI Technologies ULC
    Inventor: Nima Osqueizadeh
  • Applying a rate limit across a plurality of storage systems
    Patent number: 10671302
    Abstract: Applying a rate limit across a plurality of storage systems, including: determining a rate limit for paired storage systems; receiving, by a first storage system, an amount of I/O operations serviced by the second storage system during a previous predetermined period of time; determining whether the amount of I/O operations serviced by the second storage system is less than half of the rate limit for the paired storage systems; if so, setting local a rate limit for a next predetermined period of time for the first storage system to the difference between the rate limit for the paired storage systems and the amount of I/O operations serviced by the second storage system during the previous predetermined period of time; and otherwise, setting a local rate limit for a next predetermined period of time for the first storage system to half of the rate limit for the paired storage systems.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: June 2, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Mudit Aggarwal, Yuval Frandzel
  • Digital processing device with high connectivity and incoming/outgoing throughput embedded aboard a space platform and split up into mutually interconnected modular processing islets which are remote from one another on the scale of the platform
    Patent number: 10664423
    Abstract: A digital processing device with high input/output connectivity and modular architecture comprises a first plurality of input ports, a second plurality of output ports, and a third plurality of at least four basic elementary modules. The third plurality of the elementary modules is split up according to a partitioning of at least two sub-assemblies of module(s), at least two of which form different islets comprising at least two modules.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 26, 2020
    Assignee: THALES
    Inventors: Hélène Gachon, Norbert Venet
  • Devices and methods for transmission of events with a uniform latency on serial communication links
    Patent number: 10664435
    Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 26, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Morten Werner Lund, Lloyd Clark, Odd Magne Reitan
  • Digital bus activity monitor
    Patent number: 10664424
    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary Franklin Chard, Tpinn Ronnie Koh, Harshil Atulkumar Shah
  • Chained bus memory device
    Patent number: 10664411
    Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Victor Tsai, William Henry Radke, Bob Leibowitz
  • HyperConverged NVMF storage-NIC card
    Patent number: 10657077
    Abstract: A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or more storage devices and at least one Central Processing Unit (CPU). The bus interface is configured to connect the apparatus at least to a processor of the server. The MAC is mounted on the circuit board and is configured to connect to a communication network. The storage devices are mounted on the circuit board and are configured to store data. The CPU is mounted on the circuit board and is configured to expose the storage devices both (i) to the processor of the server via the bus interface, and (ii) indirectly to other servers over the communication network.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 19, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Avraham Ganor, Reuven Badash
  • Device and method for outputting a series of haptic effects defined in a timeline effect definition
    Patent number: 10656718
    Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 19, 2020
    Assignee: Immersion Corporation
    Inventors: Juan Manuel Cruz-Hernandez, Henrique D. Da Costa, Danny A. Grant, Robert A. Lacroix
  • Monolithically integrated system on chip for silicon photonics
    Patent number: 10649951
    Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 12, 2020
    Assignee: INPHI CORPORATION
    Inventors: Radhakrishnan L. Nagarajan, Chao Xu
  • Controlling access to previously-stored logic in a reconfigurable logic device
    Patent number: 10642492
    Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Erez Izenberg, Robert Michael Johnson, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Nafea Bshara, Christopher Joseph Pettey
  • Systems and methods for transferring data with a dual-line first-in-first-out (FIFO) memory array
    Patent number: 10621122
    Abstract: Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Lior Moheban, Ronen Goldberg, Yakov Tokar, Gregory Kovishaner, Alex Pinskiy
  • PCIe fabric connectivity expansion card
    Patent number: 10614022
    Abstract: A connectivity card insertable into a connector of a host system is provided. The connectivity card includes a plurality of Peripheral Component Interconnect Express (PCIe) connectors configured to provide external PCIe ports on the connectivity card, each of the plurality of PCIe connectors capable of carrying PCIe traffic. The connectivity card also includes a PCIe switch circuit configured to communicatively couple the plurality of connectors to a shared connectivity interface carried over a host connector of the connectivity card. The connectivity card further includes control circuitry configured to monitor for connectivity issues that arise with regard to the plurality of PCIe connectors, and responsively mitigate the connectivity issues by at least reconfiguring a communication pathway in the PCIe switch circuit for at least a portion of the PCIe traffic affected by the connectivity issues.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Liqid Inc.
    Inventors: Christopher R. Long, Andrew Rudolph Heyd, James Scott Cannata, Sumit Puri, Bryan Schramm
  • Storage system
    Patent number: 10606508
    Abstract: Provided is a storage system in which a plurality of storage controllers communicate with each other and an identifier of each storage controller is determined. The storage system includes a plurality of controllers that receive and process an input and output request specifying any of a plurality of volumes from an external device, and a plurality of switches each having a plurality of ports. The plurality of controllers are connected in parallel to the plurality of switches and communicate with each other via the plurality of switches. Each of the plurality of controllers acquires a plurality of port identifiers identifying a plurality of connected ports from the connected switches, and determines a controller identifier in the storage system based on the acquired plurality of port identifiers.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: March 31, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Shinsuke Izawa, Sadahiro Sugimoto
  • Method of processing sensing signals and related processor
    Patent number: 10606409
    Abstract: A method for processing sensing signals in a sensing system includes receiving at least one sensing signal; performing a first operation on the at least one sensing signal to determine whether the at least one sensing signal satisfies a first predetermined condition; performing a second operation on the at least one sensing signal after a second predetermined condition is determined to be satisfied, wherein the second predetermined condition comprises a condition that the first predetermined condition is determined to be satisfied, wherein the second operation provides more sensing information than the first operation; and not performing the second operation on the at least one sensing signal after a third predetermined condition is determined to be satisfied, wherein the third predetermined condition comprises a condition that the first predetermined condition is determined to be unsatisfied.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 31, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Hung-Cheng Kuo, Chun-Hung Chen, Chun-Ching Huang