Abstract: An apparatus and a method for providing a fully protective package for a flip chip with a protective shield plate and an underfill encapsulant material. The apparatus comprises a semiconductor chip electrically connected by flip chip attachment to a substrate. A shield plate is placed in contact with a back surface of the semiconductor chip. An underfill encapsulant is disposed between the semiconductor chip and the shield plate, and the substrate. A glob top encapsulant may be applied about the periphery of the upper surface of the shield plate that extends to the substrate for additional protection and/or adherence.

Abstract: A process of providing a bond pad arrangement for use with a thermocompression wire bonder including a primary bond pad for connection of an integrated circuit during a production assembly process, and a secondary test bond pad contiguous with the primary bond pad for connection of a wire to the integrated circuit. Including performing a test sequence, and removing the wire from the secondary test bond pad.

Abstract: A process wherein thermal material such as a paste or gel is confined within a paste gap between a surface of a flat cooling plate and an opposing surface of a chip mounted on a surface of a chip carrier or substrate by forming a partition, preferably in the form of a grid, at the periphery of one or more chips. The partition is located laterally in sufficient proximity to the chip and in communication with the paste gap to form a capillary and thus confine motion of a viscous thermal material to repetitive bidirectional flow out of and into the paste gap with relative motion of the chip and the surface of the flat cooling plate. The grid is preferably fitted closely within grooves formed in the surface of the flat cooling plate and preferably supported by leaf springs so that thermal material is confined within cells of the grid while providing support and/or damping of relative motion between the flat cooling plate and the substrate or carrier.

Abstract: A resin sealing type semiconductor device has first and second heat radiating portions located on opposite sides of a semiconductor element. The first heat radiating portion has an element placing surface. A plurality of leads are disposed at a given distance from the semiconductor element, and connected to the electrode pads through wires. The second heat radiating portion is located in non-contact with the semiconductor element, leads and wires. A first insulating portion is located between the first heat radiating portion and the leads. A second insulating portion is located between the second heat radiating portion and the leads. Preferably, the first insulating portion is formed continuously on one side of the first heat radiating portion, and the second insulating portion on one side of the second heat radiating portion. A space enclosed by these insulating and heat radiating portions houses the semiconductor element, the wires and the tips of the leads.

Abstract: A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.

Abstract: A semiconductor die is mounted to a die receiving area, which is defined by inner ends of conductive leads to which the die is connected. The die is temporarily retained in a substantially fixed position relative to the die receiving area by various techniques for the purpose of permitting bond wires to be attached between the conductive leads and the die. Preferred techniques include employing a mechanical chuck, dispensing an adhesive between the die and its die receiving area, and forming an ultrasonic bond between the die and the die receiving area. Once electrical connections between the die and the conductive lines are formed, the die need not be retained in a fixed position, as the electrical connections will provide sufficient support for the die. Accordingly, conventional die attach techniques, which expose the semiconductor die to substantially elevated temperatures, are avoided.

Abstract: For manufacturing a packaged semiconductor device, a lead frame with an electrically insulating strip member and a semiconductor chip is placed in a molding unit having upper and lower dies. The upper and lower dies have recessed areas for determining a size of a cavity of the molding unit different from each other, the size of the cavity being measured in a direction perpendicular to a clamping motion direction of the dies. The lead frame is positioned so that a surface of each lead with the insulating strip member applied thereto is contacted with one of the upper and lower dies having a larger recessed area and a molding line of the molding unit intersects the insulating strip member. The molding unit is closed to clamp the lead frame to depress and thrust into spaces between adjacent leads that part of the strip member which is outside the molding line and to form the cavity of the molding unit.

Abstract: A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

Abstract: A method of making a microelectronic assembly includes providing a starting subassembly having a microelectronic component with a top surface and having electrical contacts, the subassembly further including a plurality of terminals over the top surface of the component, each terminal being connected to at least one contact of the component but moveable with respect to the component; positioning a plurality of joining units each having a solid core on the terminal; providing a unit bonding material at interfaces between each core terminal; and bonding the joining units to the terminals by heating the joining units and terminals so as to convert the unit bonding material to a liquid phase without melting the cores and solidifying the unit bonding material.

Abstract: A process for manufacturing a wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.

Abstract: Disclosed is a method of forming a primer coating and an opaque coating on an integrated circuit or multichip module. First a primer coating composition is applied to a surface of the integrated circuit device or multichip module to form a primer coating that increases the resistance of the surface to thermal and mechanical damage that may occur as a result of the application of the opaque coating. An opaque coating composition is then heated to a molten state and the molten opaque coating composition is applied over the primer coating to form an opaque coating that overlies active circuitry on the surface, to prevent optical and radiation based inspection and reverse engineering of the active circuitry.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: A process within substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate.

Abstract: A process for manufacturing a modular multi-pin package for an integrated circuit die is formed of standardized parts and a redesigned, integrated circuit specific circuit substrate possessing a design pattern for providing electrical connection between die pads and output pins. The substrate includes a pattern of electrically conductive traces each terminating in a die pattern at an interior portion of the substrate and terminating in a pattern of pin connecting pads at a peripheral portion of the substrate. A pin holding frame is formed with a plurality of holes in which are inserted a selected number and pattern of package terminal pins, each having a shank protruding outwardly from the pin holder for connection to external circuits or components and each having an inner head pressed against one of the pin connecting pads of the substrate circuit traces.

Abstract: A metallization and bonding process for manufacturing a power semiconductor device includes a step of depositing a first metal layer over the entire surface of a chip; a step of selectively etching of the first metal layer to form desired patterns of metal interconnection lines between components previously defined; a step of depositing a layer of passivating material over the entire surface of the chip; a step of selectively etching of the layer of passivating material down to the first metal layer to define bonding areas represented by uncovered portions of the first metal layer; a step of depositing of a thick second metal layer over the entire surface of the chip; a step of selectively etching of the second metal layer down to the layer of passivating material to remove the second metal layer outside the bonding areas; and a step of connecting bonding wires to the surface of the second metal layer in correspondence of said bonding areas.

Abstract: The present invention discloses a method for mounting a peripheral device, such as a wafer loading device, to a semiconductor process tool that includes sensor means in the mounting surface of the peripheral device such that improper mounting between the two components can be detected and a signal can be sent out to a host computer to disable the peripheral device and to stop its motion and thus prevent any damages to the components or the substrates it carries. The peripheral device may further include spring means mounted in its mounting surface to enable the peripheral device to be pushed away from the process tool to provide a visual indication to a machine operator when the two components are not properly mounted together.

Abstract: A method of improving the yield and achievable tolerances of integrated circuits by obtaining surface measurements of non-reflective soft mounting films used in integrated circuit manufacture. The non-reflective surface of a mounting film is first rendered reflective by applying a reflective wafer atop the film surface. This reflective test wafer, which is highly plano-parallel and preferably has a thickness less than that of the ultimate product wafer, is applied to the mounting film to be measured via direct pressure whereby the reflective test wafer conforms to and takes on the surface characteristics and contours of the film. The formerly non-reflective surface of the mounting film is thereby rendered effectively reflective and thus susceptible to optical profiling and graphical and numerical recordation by a computerized interferometer in accordance with well-known techniques.

Abstract: A method for encapsulating an integrated semiconductor circuit. The semiconductor circuit is mounted onto the support surface of a so-called lead frame. Connecting wires are attached between the contact pads of the semiconductor circuit and selected parts of the lead frame. A predetermined volume of radiation-transparent plastic is supplied at a side of the semiconductor circuit opposite the side which is attached to the supporting surface, which plastic has a glass temperature lower than the temperature which is used for carrying out step c). A plastic package is produced by means of a mould, which package surrounds at least the semiconductor circuit, the supporting surface, the connecting wires and part of the lead frame.

Abstract: A method for fabricating a chip size package is provided. The method includes the step of forming a laminated substrate which consists of a dielectric layer and a highly conductive layer disposed thereon. Holes are drilled into the dielectric layer. A desired pattern is applied to the conductive layer. A chip structure is formed which consists of a silicon die and an insulating layer disposed thereon. Gold bumps are applied to the top surface of the bonding pads. The laminated substrate is bonded to the chip structure via the holes and gold bumps. A solder mask is applied over the top surface of the conductive layer of the laminated substrate so as to form selective solder areas. Finally, solder balls are attached to the selective solder areas.

Abstract: Process for manufacturing arrays of metal balls for interconnect testing and/or interconnect bonding of microelectronic devices and the like with substrates are formed by securing metal balls in predetermined patterns of apertures in an insulating membrane or film. The pattern of apertures corresponds with the pattern of metal interconnect pads on a microelectronic device or the like and the corresponding pattern of interconnect pads on the substrate. The metal ball arrays may be used for testing and/or may be heated and reflowed to bond the microelectronic device to the substrate.