Abstract: This discloses a probe structure which does not rely on cantilevered wire and which has controlled contact pressure between the probe contacts and the I/O pads on a semi-conductor chip and which comprises a plurality of conductive contact electrodes, electrically coupled to respective leads, formed, on a film stretched across a respective plurality of cavities established in a substrate. The cavities and the contact electrodes are aligned to one another and both positionally match selected I/O pads existing on a semi-conductor chip to be probed.Also disclosed is a probe utilizing a cantilevered, metalized oxide tongue extending across a cavity.

Abstract: A method and apparatus for depositing a film on a substrate by plasma-enhanced chemical vapor deposition at temperatures substantially lower than conventional thermal CVD temperatures comprises placing a substrate within a reaction chamber and exciting a first gas upstream of the substrate to generate activated radicals of the first gas. The substrate is rotated within the deposition chamber to create a pumping action which draws the gas mixture of first gas radicals to the substrate surface. A second gas is supplied proximate the substrate to mix with the activated radicals of the first gas and the mixture produces a surface reaction at the substrate to deposit a film. The pumping action draws the gas mixture down to the substrate surface in a laminar flow to reduce recirculation and radical recombination such that a sufficient amount of radicals are available at the substrate surface to take part in the surface reaction.

Abstract: A method for forming a compliant interconnect for making a temporary (or permanent) electrical connection with a semiconductor die. The compliant interconnect includes raised contacts having penetrating projections for penetrating contact locations on the die (e.g., bond pads) to a limited penetration depth. In an illustrative embodiment the raised contacts are formed on a silicon substrate as raised pillars with a hollow etched interior portion. A tip of the raised contacts is formed as a thin flexible membrane to permit a desired amount of flexure or compliancy under loading from the die held in a test fixture. In an alternate embodiment the raised contacts are formed on a hollow flexible base portion. In another alternate embodiment the raised contacts are formed on a flexible membrane mounted to a support substrate having etched pockets filled with an elastomeric material.

Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Abstract: A process for manufacturing circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g., using solder, to respective contact sites on a semiconductor chip positioned on the substrate to form part of the final package. A method for making such a package is also provided. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations, these locations, as mentioned, instead being directly connected to the chip.

Abstract: A process for manufacturing a semiconductor device comprising: a substrate having an insulating layer and a semiconductor layer lying on the insulating layer, the semiconductor layer having been divided to form a plurality of isolated semiconductor lands by trenches extending through the semiconductor layer to the insulating layer; integrated circuits formed on the respective lands; and conductors running above and across the trenches to electrically connect the integrated circuits on the isolated semiconductor lands.

Abstract: A method of forming conductive wiring on a semiconductor substrate. A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and tapered tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and tapered tungsten regions between the first and second barrier metal layers, preventing punch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.

Abstract: The present invention relates to methods of fabricating pixel electrodes for active matrix displays including the formation of arrays of transistor circuits in thin film silicon on an insulating substrate and transfer of this active matrix circuit onto an optically transmissive substrate. An array of color filter elements can be formed prior to transfer of the active matrix circuit that are aligned between a light source for the display and the array of pixel electrodes to provide a color display.

Abstract: A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

Abstract: A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.

Abstract: A reconstructed package for an integrated circuit (IC) chip and a method of re-configuring any prefabricated IC package (with or without a silicon chip and wires inside) so that an IC chip can be installed and interconnected for normal use. A pre-molded plastic or other package is abraded to expose the wire bond pads and to form a mounting surface to which a new chip may be mounted. The encapsulating material is removed without damaging the plating material on the lead frame. The new chip is then mounted onto the mounting surface and new wire bonds are connected between the new chip and the lead frame. Encapsulating material, such as epoxy, is then placed over the chip and wire bonds and cured. The invention provides an alternative process whereby the die can be encapsulated in minutes per unit.

Abstract: Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal interconnect stacks. The steps of the method comprise first providing a silicon substrate, which typically comprises an in-process integrated circuit wafer. Next, an insulating passivation layer is provided on the silicon substrate. The next step is the sputtering of a titanium layer of a given thickness over the passivation. Subsequently, an aluminum film of three times the thickness of the titanium layer is sputtered over the titanium layer. The next step comprises annealing the titanium layer and the aluminum film in situ in a metal anneal chamber to form titanium aluminide. Following the in situ anneal, the remainder of the needed aluminum is sputtered over the titanium aluminide and a further passivation layer of titanium nitride is then sputtered over the aluminum.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Abstract: According to the method of manufacturing a semiconductor device having a multilayer interconnection structure, lower wires are formed on a semiconductor substrate. Then, a first reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. After the first reflow SiO.sub.2 film is formed, heat treatment is performed at a predetermined high temperature on the semiconductor substrate on which the first reflow SiO.sub.2 film, and a second reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. The heat treatment step performed after the first reflow SiO.sub.2 film forming step and the second reflow SiO.sub.2 film forming step subsequent thereto are respectively performed at least once.

Abstract: A process of connecting a plurality of essentially identical active devices is presented for the purpose of multifunction and multiple function operation. These devices, mounted on a chip, are flip-mounted to a circuit motherboard having large passive elements. A push-pull amplifier is presented as an example in which the multiple function operation is the combining of amplifiers whose active devices are on a single chip. The electromagnetic coupling, impedance matching and signal transmission are variously provided by the use of striplines, slotlines, coplanar waveguides, and a slotline converted into a coplanar waveguide.

Abstract: A solar cell fabrication procedure is described in which a silicon substrate having a layer of silicon nitride on one side is selectively coated with a paste that contains silver metal and a glass frit. Upon heating to a temperature in excess of 760 degrees C. for a time not exceeding about 20 seconds, the glass penetrates the silicon nitride and the substrate surface is metallized by the silver metal, with the result that the finished solar cell has a fill factor of at least about 0.75 even though the paste contains no phosphorus.

Abstract: A process where in an interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

Abstract: A lead frame design and manufacturing process comprising a lead frame (18) having its internal lead fingers (20) punched out to dimensions optimized to accommodate the body size of a selected die. A die pad (30), also optimized to accommodate the body size of the selected die, is attached to the lead frame with mechanical or chemical bonding. Punches are used to punch out the internal lead pins according to selected dimensions.

Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Abstract: A process for manufacturing a flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.