Abstract: A cassette location guide bar for a loader and unloader indexer includes a guide body having pairs of guide holes which allow different sized cassettes to be interchangeably installed in the loader and unloader indexer. The guide holes are formed in the body and positioned at distances which correspond to the distance between the legs of different sized cassettes. The guide bar is inserted into and fixed onto a slot of a platform of the loader and unloader indexer.

Abstract: A method of producing a semiconductor chip on a chip carrier includes preparing a semiconductor chip having opposite front and rear surfaces and an active element on the front surface, applying solder to the rear surface of the semiconductor chip to a prescribed thickness, picking up the semiconductor chip with a collet with the rear surface facing away from the collet and exposing the solder layer to a reducing atmosphere to remove an oxide film on the surface of the solder layer, adhering the semiconductor chip to a chip carrier via the solder layer by applying heat and by applying pressure to the semiconductor chip with the collet, and cooling the chip carrier to room temperature while pressing the semiconductor chip against the chip carrier.

Abstract: A process for making a package for discrete semiconductor devices, wherein the insulating characteristics of the package are increased by introducing cuts, grooves and positioning holes in the metal plate and shaping in the retractable positioning pins of the metal plate in the molding die.

Abstract: A process for manufacturing a tape automated bonding circuit with interior sprocket holes including: a substrate; at least one conductor deposited on the substrate; a functional area on the substrate defined by a polygon surrounding the conductor with all sides of the polygon adjacent to a segment of the conductor and with interior angles of the polygon between the sides of the polygon greater or equal to ninety degrees and having at least one sprocket hole within the functional area on the substrate. The sprocket hole is used to engage and drive the tape automated bonding circuit through processing steps. In a specific embodiment the functional area on the substrate has a first set of two sprocket holes within the functional area, which are used to engage and drive the tape automated bonding circuit through processing steps.

Abstract: A method for testing leads of an integrated circuit package. The method includes a testing substrate with a plurality of conductive portions for use in connection with a test probe. The method further includes at least one compressible conductive bridge member for providing electrical contact between the leads of the integrated circuit package and the conductive portions of the testing substrate. The conductive bridge member has multiple electrically conductive wires embedded therein or secured thereto, each of the wires being parallel to one another and spaced apart from one another. The method uses a frame for retaining the conductive bridge members therein and maintaining the conductive bridge members in electrical contact with the leads of the integrated circuit package and the conductive portions of the testing substrate.

Abstract: An IC carrier on which an integrated circuit (IC) package is loaded when electric testing of the IC package is carried out is described. The present invention enables an IC package to be loaded on or unloaded from the IC carrier smoothly without bending any of closely arranged fine leads, and prevents the lead from being deformed by falling impact when it is dropped. According to the present invention, an IC carrier for an IC package having an array of leads comprises an array of socket means for mating with the array of leads, wherein selected one of said socket means differs in an inner dimension from the other ones in the same array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

Abstract: A process for making an electronic device structure which comprises a metal plate, a semiconductor material chip attached to the plate, terminal leads, interconnection wires between the leads and metallized regions of the chip, and a plastic body which encapsulates the whole with the exception of a surface of the plate and part of the leads. This structure has means of electrical connection between at least one metallized region and the metal plate which comprise at least one metal beam resting onto the plate and being attached thereto by studs integral with the plate, and at least one wire welded between a metallized region of the chip and the metal beam between the studs. At least a portion of the beam and its connection wire are encapsulated within the plastics body.

Abstract: A process wherein powder of p/n-type semiconductor thermoelectric materials expressed as (Bi, Sb).sub.2 (Te, Se).sub.3 is hot pressed under the pressure equal to or greater than 400 kgf/cm.sup.2 at 200 degrees to 400 degrees in centigrade for a time period between {(-T/5)+90} minutes and 150 minutes or at 400 degrees to 500 degrees in centigrade for a time period between 5 minutes and 150 minutes so as to increase the figure of merit by virtue of the strain left in the crystal and/or micro crystal grain, and pieces of p/n-type semiconductor thermoelectric material are assembled with electrodes so as to obtain a thermoelectric module for a high thermoelectric conversion efficiency.

Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material.In said pocket are included a type N+ cathode region and a type P anode region enclosing it.The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.

Abstract: Process for manufacturing a leadframe that is adapted to enhance the adhesion between a stage 1 and a sealing resin without decreasing the bonding strength between the stage 1 and a chip 4; and a semiconductor device constructed by using such a leadframe. The leadframe comprises a body 1 constructed from at least two kinds of layer members, 11, 12, and 13, formed from different materials and laminated one on top of the other; the materials for the layer members 11, 12, and 13 being chosen to have different etching rates. Hollow spaces 15 are formed inside the layer member having the greatest etching rate of all the layer members.

Abstract: Apparatus comprising an outside-air conditioner 2, an operation zone 4, a ceiling filter 8 such as an HEPA or ULPA filter, a fan filter unit 9 comprising a chemical filter and a draft fan arranged only on an overhead carrying apparatus 5 and storing apparatus 6 arranged in the operation zone 4 in a clean room 1 chemical mist causing chemical contamination is removed to the carrying apparatus 5 and storing apparatus 6.

Abstract: A process for manufacturing an encapsulated electronic part having a resin body and a projecting holding member removably attached to the resin body which may be made of the same resin and formed at the same time as the resin body. The encapsulated electronic part may be conveyed to a test device or to a circuit board and mounted thereon by gripping the holding member with a holding device. The holding member may have a shape conforming to the shape of the holding device and may be separated from the resin body by moving the holding device while holding the resin body stationary.

Abstract: A process wherein substrate preliminary formed with bumps by electrolytic plating or other technique is prepared. The semiconductor device is opposed to the substrate with the bumps so that the Al electrodes of the semiconductor device are aligned with respect to the bumps and brought into contact with each other. Then, the Al electrodes of the semiconductor device and the bumps are bonded together by the application of pressure and heat with an Au--Al alloy layer formed therebetween. Subsequently, the bumps are peeled off the substrate so as to be transferred to the respective Al electrodes. Thereafter, the semiconductor device is opposed to a circuit board so that the bumps are aligned with respect to the electrodes of wiring and brought into contact with them.

Abstract: A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.

Abstract: A bipolar transistor is provided whose emitter surrounds the base. The transistor has in some embodiments a high ratio of the emitter area to the base area and low collector and emitter resistances. Further, a transistor is provided in which a collector contact region is surrounded by the base. Consequently, a low collector resistance is obtained in some embodiments.

Abstract: Recesses (46) are etched into the finished peripheral boundaries of a structure formed of a generally planar electronic circuit (40) on an upper surface (42) of a wafer (44). Bonding pads (48) are deposited in the recesses (46) and interconnected to the electronic circuit (40). External leads (52) are attached to the bonding pads (48), such that the external leads (52) lie below the plane of the electronic circuit (40).

Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.

Abstract: A method for encapsulating portions of a circuit formed on a substrate. The substrate has two faces and perimeter sides. Encapsulating surrounds, in molding compound, a portion of one of the faces of the substrate and a portion of the sides of the substrate, and during encapsulation a portion of the one face of the substrate that bears conductive pads is left unencapsulated.An encapsulated circuit including a substrate having two faces and perimeter sides around the faces and a circuit formed on the substrate. The substrate also includes conductive pads that are formed on a portion of one of the faces near one of the sides and are connected to the circuit. An integrally formed encapsulating mass encapsulates all of the one face except in the region of the pads, all of the other face except in a region opposite to the region of the pads, and all of the sides.

Abstract: Process for manufacturing a high interconnection density, fine-line, superconductive printed leadframes using thick-film screen-printing techniques, or other printing techniques. Generally, a superconductive leadframe pattern is printed on a backing substrate. Once the pattern is cured, the backing substrate, or portions thereof can be removed. The backing substrate can be a "fish paper" substrate treated with a release agent, or other substrate material which can be dissolved away, etched away, or otherwise removed. Portions of the backing substrate can be used to provide mechanical integrity for the leadframe. The leadframe fingers can be printed using a superconductive paste or a superconductive precursor paste which is subsequently treated to exhibit superconductivity.

Abstract: A process for manufacturing semiconductor package of a single in-line type including a semiconductor chip, a package body for accommodating the semiconductor chip and a plurality of leads held by the package body to extend substantially perpendicularly to a bottom edge surface of the package body. The package body carries a cutout part at a predetermined position of a side edge that surrounds the package body such that the cutout part is adapted for engagement with a support leg for supporting the package body substantially upright on a substrate.