Abstract: A method of removing a component bonded to a substrate utilizes a fixture having a bore therethrough which is aligned with a bore in the substrate. A screw is advanced in the bore in the fixture to cause a push pin to contact the component and force the component away from the substrate.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.

Abstract: Process for maintaining lead positions within a glass layer of a CQFP semiconductor device by using a magnet during high temperature assembly operations. During lead embed, a magnet (46) is magnetically attached to lead frame (44). Upon reflow of a glass layer (48), leads (50) sink into the glass layer to a height controlled by the height (H) of a protrusion (52) of the magnet. A similar magnet (62) can be used to maintain the lead positions during a high temperature operation used to cure a die attach material (60). Yet another magnet (70) can be used to maintain the positions of leads (50) during a lid seal operation. A common magnet design for use in all thermal operations can instead be used. Use of the magnets restrict movement of the leads within the glass layer when the glass is in a softened state.

Abstract: According to one embodiment, the present invention provides a method for implanting halo structures into a transistor that is fabricated on a semiconductor substrate which consists of a silicon layer; a gate dielectric formed on the silicon layer; a polysilicon layer formed on the gate dielectric; and a silicon nitride layer formed over the polysilicon layer. The silicon nitride layer is patterned and removed so that a portion of the polysilicon layer is exposed. A silicon dioxide layer is then deposited over the silicon nitride layer. Next, the silicon dioxide layer is etched so that a dioxide spacer is formed on the sidewall of the silicon nitride layer. The silicon nitride layer is removed. A silicon nitride layer is deposited over the polysilicon layer and the dioxide spacer. The silicon nitride layer is etched so that nitride spacers are formed on the sidewalls of the dioxide spacer.

Abstract: A packaging method for a ball grid array (BGA) integrated circuit (IC) without utilizing a base plate as a supporting plate, and therefore reducing the thickness of the packaged BGA IC. In the method, a copper sheet is used as a supporting plate first. After resin is applied to coat a chip implanted on the copper sheet and connecting wires thereof has hardened, the hardened resin is sufficiently firm to support the IC, so the copper sheet can be etched. Accordingly, a base plate is not necessary.

Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region.

Abstract: A double spacer salicide MOS device structure and a process for preparing such a device. The double spacer salicide device has a LDD structure. The first sidewall spacer disposed adjacent to the gate structure of the MOS device is higher than the gate. During the salicide process, the first sidewall spacer is used to effectively isolate the gate from the source/drain. The second sidewall spacer disposed adjacent to the first sidewall spacer is used to form the LDD structure.

Abstract: In the substrate processing method in which substrates are immersed in processing baths holding chemicals and pure water for processing, when a substrate carrier is moved from a first processing bath to a second processing bath, the substrate carrier is moved to a second processing bath with a chemical or pure water from the first processing bath held in the substrate carrier. In subjecting substrates to chemical processing and water rinse, the substrates in the substrate carrier are carried to a next processing bath with the chemical or pure water in the first processing bath held in the substrate carrier.

Abstract: A substrate treatment apparatus according to an aspect of the invention includes a table for placing thereon an object to be treated, heating means for heating the object with the table interposed therebetween, and a plurality of support members which project from the table for supporting the object with a space interposed between the object and the table. The height of each of the support members can be varied in accordance with a surface temperature distribution of the object during treatment. A substrate treatment apparatus according to another aspect of the invention includes a table for placing thereon an object to be treated, and heating means for heating the object with the table interposed therebetween. The table has a surface thereof divided into regions of different heat radiation states in accordance with a surface temperature distribution of the object during treatment of the object.

Abstract: The present invention features a method and an article of manufacture for directly attaching silicon chips to circuit carriers. Both the method and the article of manufacture feature a dissolvable, thin wafer that is soldered first to the chip and then to the circuit board, completing the connection. The wafer article consists of embedded, spaced-apart, flexible wires that fit the connection footprints of both the chip and the carrier board. The wafer is fashioned from a matrix block having a heat-resistant, dissolvable substance which encapsulates the wires. The matrix is cut into thin slices that are wafer-thin. Each slice or wafer of the matrix carrier is then attached to a chip, using solder with an appropriate melting temperature that is thermally compatible with the chip. The solder attaches one end of the embedded wires to the chip.

Abstract: A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.

Abstract: Illustratively, the present invention includes a method of integrated circuit manufacturing which includes forming a raised topological feature upon a first substrate. A portion of the raised feature is removed, thereby exposing a cross sectional view of the raised feature with the substrate remaining substantially undamaged. The cross sectional view has a critical dimension. The critical dimension of the cross sectional view is measured using a first measuring instrument. Then the critical dimension is measured using a second measuring instrument. The measurements of the first and second measuring instruments are correlated. Then, using the second measuring instrument, raised features via plurality of second substrates are measured.

Abstract: A processing system comprising a loading/unloading section, a processing section and an interface section. The system further comprises a convey mechanism and at least two waiting sections. The convey mechanism can move in either direction between between the loading/unloading section and the interface section, for conveying objects to the processing units included in the processing section and conveying objects in either direction between the loading/unloading section and the interface section. The waiting sections are provided for temporarily holding an object before the convey mechanism conveys an object to the interface section.

Abstract: A process for manufacturing microelectronic components that can be fabricated in a facility 1 including integrated circuits on silicon wafers, flat panel displays on glass substrates or any other microelectronic components fabricated in a similar fashion, a process of constructing the facility, and the facility. The fabrication facility 1 relies on a central hub 3 from which processing areas 2 extend out radially like spokes. The processing areas 2 are arranged in a pattern so as to be served by common services which include gases, chemicals, ultra pure water, vapor exhaust, liquid waste, air conditioning, centralized vacuum, centralized clean compressed air, hot water, steam, natural gas, power including emergency, conditioned, and unconditioned power, and process cooling water.

Abstract: An integrated wafer loader is provided for use with a vacuum process chamber. At least one semipermeable membrane provided in the separator between upper and lower chambers of a load lock permits air flow while preventing particulate matter transfer. A micro-environment container is sealed within the upper chamber and a vacuum simultaneously produced in both upper and lower chambers. A movable carrier plate opens the micro-environment container and removes a cassette of wafers from therein and into the lower chamber. The micro-environment container remains supported by the separator and forms an impermeable barrier between the chambers. Wafers are transferred from the cassette to the process environment, and returned to the cassette after processing has been completed. The carrier plate returns the cassette containing the processed wafers to the micro-environment container for removal from the load lock chamber.

Abstract: Disclosed herein are a method of fabricating a power semiconductor device having joiners that (205) vertically extend from outer sides of leads (203, 204) of a tie bar (201) of a power circuit lead frame (20) respectively, while joiners (308) vertically extend from outer sides of leads (303, 307) of a tie bar (301) of a control circuit lead frame (30) respectively to be opposed thereto. Forward end portions (205a) of the joiners (205) are joined to rear surfaces of forward end portions (308a) of the joiners (308) at a device center portion.

Abstract: A fabrication method for manufacturing a monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Abstract: To assure that a loop height remains constant even if the wiring distance should vary and no slack is generated in the hypotenuse of the bonded wire: the length of the covered wire required for a next wiring operation is set by a formula which combines a first-order function of a wiring distance, a first-order reciprocal function of the wiring distance and a constant; the covering-film at the corresponding position is removed; and the exposed-core portion of the covered wire from which the covering-film has been removed is bonded to the lead of a lead frame with the loop height fixed even if the wiring distance should change.

Abstract: A method for manufacturing tantalum capacitors includes preparing a tantalum compact by cold pressing tantalum powder, placing the compact, along with loose refractory metal powder, in a microwave-transparent casket to form an assembly, and heating the assembly for a time sufficient to effect at least partial sintering of the compact and the product made by the method.