Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer.

Abstract: A process in which a plurality of IC chips are stacked in a unitary structure having a novel method of exposing leads on the access plane of the stack. After a layer of dielectric material has been formed on the access plane, trenches (preferably trenches) are formed, e.g., by wet lithographic processing, which expose the access plane leads. Thereafter terminals are formed on the access plane in contact with the leads. At the wafer level, layers of dielectric material are deposited which are sufficiently thick to permit the subsequent forming of trenches in the access plane dielectric without uncovering any of the silicon of the IC chips.

Abstract: A TAB semiconductor device (98) is manufactured with a TAB tape (62') which provides an intrinsic standoff for the device. The tape (62') has a carrier film (66'), having at least one cavity, and a plurality of conductors (64) on the top surface of the carrier film. A semiconductor die (42) is substantially centered either inside or below the cavity in the film. The conductors overlie bonding sites (44) on the active surface of the die. Inner-lead-bonds are made between the conductors and the bonding sites, wherein the conductors bend at the edges (65') of the cavity in order to contact the bonding sites, thus concurrently achieving a downset during the action of bonding. An encapsulant (99) provides protection to the die, the inner-lead-bonds, and a portion of the conductors.

Abstract: In a nonvolatile semiconductor memory device and a method of producing the same, the nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of spaced source/drain diffusion layers of a second conductivity type different from the first conductivity type, a floating gate electrode formed on a channel region disposed between the pair of source/drain diffusion layers in the surface of the semiconductor substrate in an insulated relationship with the channel region, and a control gate electrode formed on the floating gate electrode in on insulated relationship with the floating gate electrode wherein a part of the control gate electrode to extend beyond a side of the floating gate electrode to an underside thereof.

Abstract: A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the first and the second major surfaces of a blank. The first and the second major surfaces of the blank are etched through the first and the second resist pattern by a first etching process using a first etchant to form a first recess corresponding to the first opening and second recesses corresponding to the second recesses in the first and the second major surfaces, respectively. The first recess is filled up with an etch-resistant layer. The second major surface is etched through the second resist pattern by a second etching process using a second etchant so that portions of the blank corresponding to the second openings of the second resist pattern are etched through to form the tips of the inner leads.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: Interconnects (22 and 32) are formed within an insulating base material of a first substrate. Trenches (54) and portions of an insulating layer (52) are formed within a second substrate (50). The two substrates are bonded by fusion. The second substrate is polished back to form semiconductor islands (81-83) over the first substrate. Active regions of transistors are formed within the islands (81-83). Conductive plugs (131-134) are made between portions of the active regions and interconnects (22, 32, and 141) that underlie or overlie the semiconductor islands (81-83). Embodiments of the present invention allow higher component density, better thickness control for SOI regions, and lower leakage current compared to SOI layers that use LOCOS-type field isolation.

Abstract: A rapid thermal anneal (RTA) process minimizes the intermixing of materials between a bump and a bonding pad so as to provide for a more reliable and durable interconnect between the bump and the bonding pad and so as to allow the probing of wafers prior to bumping. A barrier layer is formed over the bonding pads of devices formed over a semiconductor substrate. Bumps are then formed over the bonding pads and are annealed for a short time at a high temperature so as to soften the bumps for later assembly in a semiconductor package. As a result of this quick annealing process, the intermixing of materials between the bumps and the bonding pads is minimized. This is so despite any decreased step coverage of the barrier layer over probe marks on the bonding pads which resulted from testing the wafer. Accordingly, wafers may now be tested prior to bumping, thus saving the cost, time, and process steps typically incurred in bumping wafers having a zero or low yield of properly functioning semiconductor devices.

Abstract: A process for manufacturing bonding pad adapted for use with an aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick aluminum alloy bonding pad.