Patents Examined by David H. Malzahn

Patent number: 10331406Abstract: A data processing apparatus and method of operating a data processing apparatus are disclosed. Comparisons are made between first and second floatingpoint operands received. A more significant portion of the first floatingpoint operand and of the second floatingpoint operand are subject to comparison. The more significant portion of the first floatingpoint operand minus a least significant bit in the more significant portion is subject to comparison with the more significant portion of the second floatingpoint operand. A less significant portion of the first floatingpoint operand and of the second floatingpoint operand are also subject to comparison. In dependence on the outcome of these comparisons, rightshift circuitry is used selectively to perform a 1bit right shift on a difference calculated between the first floatingpoint operand and the second floatingpoint operand.Type: GrantFiled: November 17, 2017Date of Patent: June 25, 2019Assignee: ARM LimitedInventors: David Raymond Lutz, Thomas Gilles Tarridec

Patent number: 10331412Abstract: A device for random number generation based on an optical process of quantum nature, including a light source emitting photons randomly, a light detector adapted to absorb the randomly emitted photons and to measure a number n of photons produced by the light source in a time interval T, and a randomness extractor. The detector includes a photon sensor acting as a photontoelectron converter, an amplifier for converting the electron signal received from the photon sensor into a voltage and amplifying the voltage signal, as well as an analogtodigital converter for processing the amplified signal received from the amplifier by encoding the amplified signal into digital values and sending these digital values to the randomness extractor for further processing such as to produce quantum random numbers (QRNs) based on the number of photons produced by the light source in a time interval T.Type: GrantFiled: July 25, 2017Date of Patent: June 25, 2019Assignee: Université de GenèveInventors: Bruno Sanguinetti, Anthony Martin, Nicolas Gisin, Hugo Zbinden

Patent number: 10331411Abstract: Systems and methods for generating random bits by using physical variations present in material samples are provided. Initial random bit streams are derived from measured material properties for the material samples. In some cases, secondary random bit streams are generated by applying a randomness extraction algorithm to the derived initial random bit streams.Type: GrantFiled: December 1, 2015Date of Patent: June 25, 2019Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Jennifer F. Schumacher, Glenn E. Casner, Yanina Shkel, Andrew P. Bonifas, Anthony J. Sabelli, Brian J. Stankiewicz, John A. Wheatley, Ravishankar Sivalingam, Robert W. Shannon

Patent number: 10331408Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a userdefined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.Type: GrantFiled: November 8, 2017Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller

Patent number: 10324687Abstract: Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.Type: GrantFiled: November 9, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael K. Gschwind

Patent number: 10318290Abstract: A first floatingpoint operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floatingpoint operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floatingpoint operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: GrantFiled: May 24, 2017Date of Patent: June 11, 2019Assignee: ARM Finance Overseas LimitedInventor: David YiuMan Lau

Patent number: 10311127Abstract: Systems and methods for multiplying a sparse matrix by a vector using a single instruction multiple data (SIMD) architecture are provided. An example method includes sorting rows of the sparse matrix by a number of nonzero elements in the rows to generate sorted rows. The sorted rows are split to generate groups of the sorted rows. The number of rows in each group of the sorted rows is equal to the number of rows updated in parallel. The method allows for packing the sorted rows in each of the groups to generate packed rows. Each of the packed rows within the same group has the same length. Per clock cycle, C elements of the packed rows and data for selecting elements of the vector are provided to computational units in the SIMD architecture, where C is the number of computational units.Type: GrantFiled: October 27, 2017Date of Patent: June 4, 2019Assignee: Knowles Electronics, LLCInventor: Leonardo Rub

Patent number: 10296556Abstract: A system and method for efficient sparse matrix processing are provided in one embodiment. A compressed representation of a sparse matrix, the sparse matrix including one or more nonzero entries in one or more of a plurality of portions of the matrix, is obtained by at least one server including one or more streaming multiprocessors, each of the streaming multiprocessors including one or more graphics processing unit (GPU) processor cores. Each of the portions are assigned into one of a plurality of partitions based on a number of the nonzero entries in that portion. For each of the partitions, a predefined number of the GPU processor cores are assigned for processing each of the portions assigned to that partition based on the numbers of the nonzero entries in the portions assigned to that partition. For each of the partitions, each of the portions associated with that partition are processed.Type: GrantFiled: September 7, 2017Date of Patent: May 21, 2019Assignee: Palo Alto Research Center IncorporatedInventor: Rong Zhou

Patent number: 10296294Abstract: Disclosed herein is a computer implemented method for performing multiplyadd operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiplyadd operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiplyadd operations.Type: GrantFiled: February 15, 2018Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Tina Babinsky, Michael Klein, Cedric Lichtenau, Silvia M. Mueller

Patent number: 10289386Abstract: A multiplier unit may be configured to generate a final approximation of an iterative arithmetic operation performed on two operands. Circuitry coupled to the multiplier unit may perform a shift operation and a mask operation on the final approximation to generate shifted and unshifted approximations, respectively. The circuitry may generate a first remainder using the unshifted approximation and a sign value of a second remainder using the first remainder. Using the sign value of the second remainder, the circuitry may perform a rounding operation on the shifted approximation to generate a final answer.Type: GrantFiled: April 21, 2016Date of Patent: May 14, 2019Assignee: Oracle International CorporationInventors: Josephus Ebergen, Christopher Olson, Dmitry Nadehzin, David Rager, Austin Lee

Patent number: 10289331Abstract: Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multicore processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical prefetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level prefetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.Type: GrantFiled: September 26, 2018Date of Patent: May 14, 2019Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Bruce J. Chang, Fred Tsai, John D. Pape

Patent number: 10277716Abstract: An approach for multistream data compression comprises receiving packets of a data stream, wherein the packets comprise respective packets of source data streams compressed on an aggregate basis and in a successive order. A one of the packets is decompressed, and a determination is made whether the packet has been received in a proper order of succession compared to the successive order of compression. When it is determined that the packet has been received in the proper order, the packet is stored at a next location in a decompressor cache. When it is determined that the packet has not been received in the proper order, the packet is stored at a location in the decompressor cache, allowing for subsequent storage of one or more further packets in the proper order of succession, wherein the further packets were processed via the compression process before, but were received after, the one packet.Type: GrantFiled: October 25, 2016Date of Patent: April 30, 2019Assignee: Hughes Network Systems, LLCInventors: Udaya Bhaskar, Douglas Dillon

Patent number: 10268452Abstract: A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed, and a controller coupled to the true random number generator and the pseudo random number generator to (1) generate a new true random number concurrently with the operation of the pseudo random number generator, and storing the new true random number, and (2) reseed the pseudo random number generator with the new true random number.Type: GrantFiled: January 3, 2017Date of Patent: April 23, 2019Assignee: Synopsys, Inc.Inventors: Scott Andrew Hamilton, Neil Farquhar Hamilton

Patent number: 10268450Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.Type: GrantFiled: September 6, 2017Date of Patent: April 23, 2019Assignee: Imagination Technologies LimitedInventor: Tim Lee

Patent number: 10255041Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for performing multiprecision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiplyadd, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64bit multiplication when NewtonRaphson, divide and square root operations are performed.Type: GrantFiled: June 13, 2017Date of Patent: April 9, 2019Assignee: Imagination Technologies LimitedInventor: Leonard Rarick

Patent number: 10235343Abstract: A circuit for fast matrixvector multiplication and a method for constructing that circuit are provided, comprising processing a matrix to obtain a pair matrix, which is then used to construct a circuit.Type: GrantFiled: November 7, 2017Date of Patent: March 19, 2019Inventor: Pavel Dourbal

Patent number: 10235138Abstract: An instruction configured to perform a plurality of functions is executed. Based on a function code associated with the instruction having a selected value, one or more inputs of the instruction are checked to determine which one or more functions of the plurality of functions are to be performed. Based on a first input of the one or more inputs having a first value, a function of providing raw entropy is performed, in which the providing of raw entropy includes storing a number of raw random numbers. Further, based on a second input of the one or more inputs having a second value, a function of providing conditioned entropy is provided, in which the providing of conditioned entropy includes storing a number of conditioned random numbers.Type: GrantFiled: September 30, 2016Date of Patent: March 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Bernd Nerz, Timothy J. Slegel, Tamas Visegrady, Christian Zoellin

Patent number: 10228939Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.Type: GrantFiled: December 14, 2016Date of Patent: March 12, 2019Assignee: Oracle International CorporationInventors: Jeffrey S. Brooks, Austin Lee

Patent number: 10223068Abstract: Hardware logic arranged to normalize (or renormalize) an nbit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.Type: GrantFiled: June 28, 2017Date of Patent: March 5, 2019Assignee: Imagination Technologies LimitedInventor: Theo Alan Drane

Patent number: 10224954Abstract: Embodiments of an instruction, its operation, and executional support for the instruction are described. In some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a single precision floating point data element of a least significant packed data element position of the identified packed data source operand to a fixedpoint representation, store the fixedpoint representation as 32bit integer and a 32bit integer exponent in the two least significant packed data element positions of the identified packed data destination operand, and zero of all remaining packed data elements of the identified packed data destination operand.Type: GrantFiled: September 29, 2017Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Venkateswara Madduri, Elmoustapha OuldAhmedVall, Robert Valentine, Jesus Corbal, Mark Charney