Abstract: A method includes detecting noise in a laser output of a heat assisted magnetic recording device. The noise is converted into an electrical signal including a numerical value. A least significant digit of the numerical value is selected. The least significant digit is concatenated with another least significant digit from another detecting of another noise in another laser output to form a number.

Abstract: A calculating device includes a key input unit, a display and a processor. The processor performs: calculating a payment data item from input calculation data including numerical data items and operation data items; in the case where input of a first deposit data item and an instruction of a change function are received, controlling the display to display a calculation result data item obtained by subtracting the payment data item from the first deposit data item, as a first change data item; and in the state where the display displays the first change data item, even though the input calculation data are not re-input, if a second deposit data item and an instruction of the change function are received, controlling the display to display a calculation result data item obtained by subtracting the payment data item from the second deposit data item, as a second change data item.

Abstract: The disclosed method may include (1) receiving a precision level of each weight associated with each input of a node of a computational model, (2) identifying, for each weight, one of a plurality of multiplier groups, where each multiplier group may include a plurality of hardware multipliers of a corresponding bit width, and where the corresponding bit width of the plurality of hardware multipliers of the one of the plurality of multiplier groups may be sufficient to multiply the weight by the associated input, and (3) multiplying each weight by its associated input using an available hardware multiplier of the one of the plurality of multiplier groups identified for the weight. Various other processing elements, methods, and systems are also disclosed.

Abstract: Random number generator systems and method for tuning a randomness characteristic of the system are described. The random number generator system includes at least one programmable metallization cell (PMC) device and is configured to provide a random output word based on random telegraph noise caused by the at least one PMC device.

Abstract: A partitioned block frequency domain adaptive filter device includes a frequency domain adaptive filter configured for filtering a frequency domain representation of a time domain input signal depending on a set of filter coefficients consisting of a plurality of blocks of filter coefficients in order to produce a filtered signal; a plurality of parallel arranged filter update blocks; wherein each of the filter update blocks includes an adaptation module configured for executing an adaptation sequence including the steps of calculating an approximation of a constrained gradient update for the filter coefficients of the respective block of filter coefficients, and calculating a cumulative error introduced on the unconstrained gradient update; wherein each of the filter update blocks includes a correction module configured for executing a correction sequence including the steps of calculating a corrected constrained gradient update for the filter coefficients of the respective block of filter coefficients.

Abstract: A configurable processor comprises a memory die and a logic die. The memory die comprises a programmable memory array for storing a look-up table (LUT) for a mathematical function, while the logic die comprises an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.

Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

Abstract: Disclosed herein is a true random number generator (TRNG). The TRNG includes a cavity filled with tritium and an electronic sensor constructed to detect energy from the decay of the tritium. The sensor produces a signal for the detected energy, and an amplifier amplifies the signal while a filter filters the signal. A processor (a) determines whether the signal represents decay events for tritium; (b) sets a timer to determine the time period between decay events; (c) based on the time period in step (b), assigns a value of a 0 or a 1; (d) stores the value in a memory; (e) repeats steps (b)-(d), resulting in a string of values; and (f) generates a true random number based on the string of values. This TRNG may be formed on an integrated circuit.

Abstract: Among the embodiments disclosed herein are quantum circuits (and associated compilation techniques) for performing Shor's quantum algorithm to factor n-bit integers. Example embodiments of the circuits use only 2n+2 qubits. In contrast to previous space-optimized implementations, embodiments of the disclosed technology feature a purely Toffoli-based modular multiplication circuit. Certain other example modular multiplication circuits disclosed herein are based on an (in-place) constant-adder that uses dirty ancilla qubits to achieve a size in (n log n) and a depth in (n).

Abstract: An apparatus for modifying a sampling rate includes a forward transformer for forming a first version of a spectrogram by means of transformation with a first transformation length from an information signal with a first sampling rate. The apparatus includes a processor for forming a second version of the spectrogram with a lower bandwidth than the first version. The apparatus includes a reverse transformer for forming a coarsely pre-modified information signal with a second sampling rate that is reduced with respect to the first sampling rate, by means of reverse transformation of the second version of the spectrogram with a second transformation length that is reduced with respect to the first transformation length. The apparatus includes a time domain interpolator for acquiring an information signal with a third sampling rate that is modified with respect to the second sampling rate, by means of interpolation of the pre-modified information signal.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

Abstract: A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h?1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

Abstract: A system performs convolution computing in either a matrix mode or a filter mode. An analysis module generates a mode select signal to select the matrix mode or the filter mode based on results of analyzing convolution characteristics. The results include at least a comparison of resource utilization between the matrix mode and the filter mode. A convolution module includes processing elements, each of which further includes arithmetic computing circuitry. The convolution module is configured according to the matrix mode for performing matrix multiplications converted from convolution computations, and is configured according to the filter mode for performing the convolution computations.

Abstract: An optical system uses a multi-layered birefringent structure that receives an input beam that may be non-coherent or coherent, and produces a randomization energy from the input beam, by creating birefringent induced beam subdivisions as the beam passes through each birefringent layer, where after the beam has passed through a threshold number of birefringent layers, a randomized energy distribution is created. That randomized energy distribution is read by a photodetector and converted into a random number by a randomization processing device.

Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

Abstract: Provided are a true random number generator and an oscillator. The random number generator includes an oscillator configured to output signals and oscillate a random number of times until phases of the signals being output are inverted with respect to each other after initialization, and a counter configured to count the number of oscillations. The counted number of oscillations is used as a seed for generating a random number.

Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.