Abstract: An approach for multi-stream data compression comprises receiving packets of a data stream, wherein the packets comprise respective packets of source data streams compressed on an aggregate basis and in a successive order. A one of the packets is decompressed, and a determination is made whether the packet has been received in a proper order of succession compared to the successive order of compression. When it is determined that the packet has been received in the proper order, the packet is stored at a next location in a decompressor cache. When it is determined that the packet has not been received in the proper order, the packet is stored at a location in the decompressor cache, allowing for subsequent storage of one or more further packets in the proper order of succession, wherein the further packets were processed via the compression process before, but were received after, the one packet.

Abstract: A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed, and a controller coupled to the true random number generator and the pseudo random number generator to (1) generate a new true random number concurrently with the operation of the pseudo random number generator, and storing the new true random number, and (2) reseed the pseudo random number generator with the new true random number.

Abstract: A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h-1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64-bit multiplication when Newton-Raphson, divide and square root operations are performed.

Abstract: An instruction configured to perform a plurality of functions is executed. Based on a function code associated with the instruction having a selected value, one or more inputs of the instruction are checked to determine which one or more functions of the plurality of functions are to be performed. Based on a first input of the one or more inputs having a first value, a function of providing raw entropy is performed, in which the providing of raw entropy includes storing a number of raw random numbers. Further, based on a second input of the one or more inputs having a second value, a function of providing conditioned entropy is provided, in which the providing of conditioned entropy includes storing a number of conditioned random numbers.

Abstract: A circuit for fast matrix-vector multiplication and a method for constructing that circuit are provided, comprising processing a matrix to obtain a pair matrix, which is then used to construct a circuit.

Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Abstract: Embodiments of instructions and methods of execution of said instructions and resources to execute said instructions are detailed. For example, in an embodiment, a processor comprising: decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a data element from a least significant packed data element position of the identified packed data source operand from a fixed-point representation to a floating point representation, store the floating point representation into a 32-bit least significant packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand is described.

Abstract: Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

Abstract: Embodiments of an instruction, its operation, and executional support for the instruction are described. In some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a single precision floating point data element of a least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as 32-bit integer and a 32-bit integer exponent in the two least significant packed data element positions of the identified packed data destination operand, and zero of all remaining packed data elements of the identified packed data destination operand.

Abstract: An aspect includes fetching a computer instruction, the fetching by an instruction fetch unit. It is determined that the instruction is a decimal divide instruction that specifies a decimal divisor and a decimal dividend. The decimal divisor is converted into a floating-point divisor and the decimal dividend is converted into a floating-point dividend. A floating-point division of the floating-point dividend by the floating-point divisor is performed by an instruction execution unit. It is determined that the floating-point division resulted in a quotient overflow. A reduced size floating-point dividend is generated based on the quotient overflow, the floating-point divisor, and the floating-point dividend. The floating point division of the reduced size floating-point dividend by the floating-point divisor is performed by the instruction execution unit, and a specified number of rightmost bits of the result is output as the quotient.

Abstract: Apparatuses and methods of manufacturing same, systems, and methods for generating a starting estimate for radix-16 square root iterative calculation using hardware, including a radix-4 partial remainder-divisor (PD) table, which is used for both division and square root operations, are described. In one aspect, a part of a radicand for a radix-16 square root iterative operation is used to determine column/root and row/partial radicand values, which are then used to determine a starting estimate from a radix-4 PD table for the radix-16 square root iterative operation.

Abstract: A median filter device is provided with a reordered circuit, a comparison circuit and a data refresh circuit on the basis of the conventional data buffer circuit and data register circuit. The reorder circuit re-sorts the signal data stored in the data buffer circuit in a preceding clock cycle according to their numerical values. The comparison circuit compares the new signal datum entered in the current clock cycle with the signal data already stored to generate a median. The data refresh circuit updates the signal codes stored in the data register circuit with the signal codes corresponding to the new signal data, for calculation of the median in a following clock cycle. The length of the data buffer circuit and data register circuit can be reduced from N signal data to N?1 signal data, which achieves less data storage capacity, smaller circuit area, easier data processing and higher operation efficiency.

Abstract: Lossless content-aware compression and decompression techniques are provided for floating point data, such as seismic data. A minimum-length compression technique exploits an association between an exponent and a length of the significand, which corresponds to the position of the least significant bit of the significand. A reduced number of bits from the significand can then be stored. A prediction method is also optionally previously applied, so that residual values with shorter lengths are compressed instead of the original values. An alignment compression technique exploits repetition patterns in the floating point numbers when they are aligned to the same exponent. Floating point numbers are then split into integral and fractional parts. The fractional part is separately encoded using a dictionary-based compression method, while the integral part is compressed using a delta-encoding method.

Abstract: In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

Abstract: Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to output one or more of the respective values. The Galois-field reduction circuitry also includes exclusive-OR circuitry for combining output of the plurality of memories with in-field bits of said expansion value. There are also a method of operating such Galois-field reduction circuitry to reduce a Galois-field expansion value, a programmable integrated circuit device incorporating the circuitry, a method of performing a Galois-field multiplication operation on such a programmable integrated circuit device, and a method of configuring a programmable integrated circuit device to perform such a Galois-field multiplication operation.

Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.

Abstract: Heterogeneous hardware accelerator architectures for processing sparse matrix data having skewed non-zero distributions are described. An accelerator includes sparse tiles to access data from a first memory over a high bandwidth interface and very/hyper sparse tiles to randomly access data from a second memory over a low-latency interface. The accelerator determines that one or more computational tasks involving a matrix are to be performed, partitions the matrix into a first plurality of blocks that includes one or more sparse sections of the matrix, and a second plurality of blocks that includes sections of the matrix that are very- or hyper-sparse. The accelerator causes the sparse tile(s) to perform one or more matrix operations for the computational task(s) using the first plurality of blocks and further causes the very/hyper sparse tile(s) to perform the one or more matrix operations for the computational task(s) using the second plurality of blocks.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract: Embodiments relate to a configurable convolution engine that receives configuration information to perform convolution and other deep machine learning operations on streaming input data of various formats. The convolution engine may include two convolution circuits that each generate a stream of values by applying convolution kernels to input data. The stream of values may each define one or more channels of image data. A channel merge circuit combines the streams of values from each convolution circuit in accordance with a selected mode of operation. In one mode, the first and second streams from the convolution circuits are merged into an output stream having the combined channels of the first and second streams in an interleaved manner. In another mode, the first stream from the first convolution circuit is fed into the input of the second convolution circuit.