Abstract: An instruction to perform a sign operation of a plurality of sign operations configured for the instruction. The instruction is executed, and the executing includes selecting at least a portion of an input operand as a result to be placed in a select location. The selecting is based on a control of the instruction, in which the control indicates a user-defined size of the input operand to be selected as the result. A sign of the result is determined based on a plurality of criteria, including a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value. The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment.

Abstract: In one embodiment, a matrix operation associated with a plurality of input matrices may be performed. The plurality of input matrices may be partitioned into a plurality of input partitions, wherein the plurality of input matrices is partitioned based on a number of available processing elements. The plurality of input partitions may be distributed among a plurality of processing elements, wherein each input partition is distributed to a particular processing element of the plurality of processing elements. A plurality of partial matrix operations may be performed using the plurality of processing elements, and partial matrix data may be transmitted between the plurality of processing elements while performing the plurality of partial matrix operations. A result of the matrix operation may be determined based on the plurality of partial matrix operations.

Abstract: A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

Abstract: A processor for floating point underflow detection includes circuitry to decode a first instruction and a floating point unit. The decoded instruction, when executed by the processor, may be for performing a fused multiply-add (FMA) operation. The floating point unit includes circuitry to determine a non-normalized result of the first instruction based on a first input, a second input, and a third input. The floating point unit further includes circuitry to determine whether underflow exists in the non-normalized result based on a first exponent of the first input, a second exponent of the second input, and a third exponent of the third input.

Abstract: Examples relate to calculating normalize metrics. The examples disclosed herein calculate respective normalized first metric values for each of a plurality of first metric values that are on a time scale and respective normalized second metric values for each of the plurality of raw second metric values that are on the time scale, where the plurality of first metric values are associated with a first metric, and the plurality of second metric values are associated with a second metric. An extremum of the normalized first metric value and the normalized second metric value at each time of the time scale is averaged to calculate a plurality of extremum baseline values. Examples herein calculate a plurality of sleeve values of the plurality of extremum baseline values based on a standard deviation of the plurality of extremum baseline values.

Abstract: A data processing apparatus is provided, to calculate an at least partial square root of a floating point number having an exponent and significand. Recurrence circuitry performs one or more iterations of an iterative square root operation, each of the one or more iterations receiving an input at least partial square root and an input remainder to produce the at least partial square root and a remainder of performing the iterative square root operation. The recurrence circuitry provides the at least partial square root and the remainder as the input at least partial square root and the input remainder for a subsequent iteration of the iterative square root operation. The recurrence circuitry includes initialization circuitry to provide the at least partial square root and the remainder after at least an initial iteration of the one or more iterations.

Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and denormal inputs and outputting normal and denormal results, and where a rounding module is used advantageously to reduce operational latency of the circuit.

Abstract: A processor includes circuitry to decode at least one instruction and an execution unit. The decoded instruction may compute a floating point result. The execution unit includes circuitry to execute the instruction to determine the floating point result, compute the amount of precision lost in a mantissa of the floating point result, compare the amount of precision lost to a numeric accumulation error precision threshold, determine whether a numeric accumulation error occurred based on the comparison, and write a value to a flag. The amount of precision lost corresponds to a plurality of bits lost in the mantissa of the floating point result. The value to be written to the flag may be based on the determination that the numeric accumulation error occurred. The flag may be for notification that the numeric accumulation error occurred.

Abstract: A model calculation unit for calculating a data-based function model in a control unit is provided, the model calculation unit having a processor core which includes: a multiplication unit for carrying out a multiplication on the hardware side; an addition unit for carrying out an addition on the hardware side; an exponential function unit for calculating an exponential function on the hardware side; a memory in the form of a configuration register for storing hyperparameters and node data of the data-based function model to be calculated; and a logic circuit for controlling, on the hardware side, the calculation sequence in the multiplication unit, the addition unit, the exponential function unit and the memory in order to ascertain the data-based function model.

Abstract: An apparatus for testing a random number generator includes a correlation test circuit and a randomness determination circuit. The correlation test circuit extracts a first plurality of bit pairs each including two bits spaced apart from each other by a first distance in a bit stream generated by the random number generator, obtains a first sum of differences between respective two bits of the first plurality of bit pairs, and obtains a second sum of differences between respective two bits of a second plurality of bit pairs, the second plurality of bit pairs each including two bits spaced apart from each other by a second distance, different from the first distance, in the bit stream. The randomness determination circuit determines a randomness of the bit stream, based on the first sum and the second sum.

Abstract: A random number generator includes a photon source and one or more photon detectors of the SPAD type (311) configured to detect a photon flow equal to ?, wherein the photons are generated by the photon source. The random number generator furthermore includes an electronic sampler. The electronic sampler is configured in such a way as to detect the arrival time t of a photon incident on each SPAD photon detector (311) for each one of the observation windows Tw, and are also configured in such a way as to convert the arrival time t into a binary sequence. In the generator of the invention the photon source and the electronic sampler are configured in such a way that the product ?*Tw is lower than or equal to 0.01.

Abstract: A device includes parallel connected ring oscillators, a pseudo random number generator (PRNG), and a configuration circuit. The parallel connected ring oscillators include a first and second ring oscillator. The PRNG is configured to generate pseudo random bits at every cycle. The configuration circuit is configured to receive and parse the pseudo random bits to generate and distribute a first configuration value and second configuration value based on the pseudo random bits. The first ring oscillator is configured according to the first configuration value. The second ring oscillator is configured according to the second configuration value.

Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.

Abstract: A data storage method includes storing a plurality of pieces of 2-bit wide ternary data in one word, each of the plurality of pieces of 2-bit wide ternary data indicating +1 when a first bit indicates a first value, indicating ?1 when a second bit indicates the first value, and indicating 0 when both the first bit and the second bit indicate a second value.

Abstract: Integrated circuits with specialized processing blocks that can support both fixed-point and floating-point operations are provided. A specialized processing block of this type may include partial product generators, compression circuits, and a main adder. The main adder may include a high adder, a middle adder, a low adder, floating-point rounding circuitry, and associated selection circuitry. The middle adder may include prefix networks for outputting generate and propagate vectors, and redundant LSB processing logic for outputting LSB generate and propagate bits. The middle adder may include additional logic circuitry for generating a sum output, a sum-plus-1 output, and a sum-plus-2 output. The specialized processing block may further include accumulation circuitry for support multiply-accumulation functions for any suitable number of channels.

Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.

Abstract: A magnetic random number generator is disclosed. The magnetic random number generator comprises: a) a Hall cross structure comprising at least one magnetic nanowire with perpendicular magnetic anisotropy; b) an in-plane pulsed current generator operable to generate stochastic nucleation of domain walls (DWs) in the Hall cross structure; and c) a sensor configured to measure a parameter of the Hall cross structure upon DW nucleation, wherein said parameter has a value representing a random number. A greater number of Hall cross structures may be employed to generate a random number having a greater number of bits.

Abstract: A method of calculating data includes acquiring a difference between first data that is input and second data that was previously stored; determining a method of generating third data corresponding to a result of a calculation of the first data based on the difference; and performing a calculation corresponding to the determined method using a calculator.

Abstract: Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical pre-fetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level pre-fetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.

Abstract: An improved biquad infinite impulse response filter is shown that may be implemented in a very large instruction word digital signal processor as well as in other processing circuitry. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles.