Patents Examined by David Hardy
  • Patent number: 6501136
    Abstract: A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diffusion edges are effectively continuous along the gate/channel layout, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. In addition, multiple poly-gate extensions are incorporated to reduce the gate resistance, thereby minimizing the propagation delay of the gate signal.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: December 31, 2002
    Assignee: Winbond Electronics Corporation
    Inventor: Shi-Tron Lin
  • Patent number: 6433400
    Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: August 13, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Derick J. Wristers
  • Patent number: 6424003
    Abstract: An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: July 23, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: Xiao Yu Li, Sunil D. Mehta, Christopher O. Schmidt
  • Patent number: 6355973
    Abstract: A semiconductor die is enveloped by an ambient gas that will react to the presence of a particular wave length of light. A laser beam is focused on the edge of the die to deposit a dielectric coating. The laser beam or the die is rotated until the dielectric coating covers the entire die edge. The dielectric coating acts as a seal that is impervious to water and other contamination that can reduce the die reliability. The dielectric coating also electrically insulates the die from its surroundings.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 12, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kendall Scott Wills, Paul Anthony Rodriguez
  • Patent number: 6346715
    Abstract: A semiconductor device including a control circuit for carrying out gamma correction of a supplied signal and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs and are a integrally formed on the same insulating substrate. A semiconductor display device including a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal. The plurality of TFTs, the driver, the control circuit, and the memory are integrally formed on the same insulating substrate.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: February 12, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 6268658
    Abstract: A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: July 31, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiromi Todorobaru, Hideo Miura, Masayuki Suzuki, Shinji Nishihara, Shuji Ikeda, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Atushi Ogishima, Hiroyuki Uchiyama, Sonoko Abe
  • Patent number: 6255702
    Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: July 3, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Masayuki Nakano, Shigeki Hayashida, Seizou Kakimoto, Toshimasa Matsuoka
  • Patent number: 6242792
    Abstract: A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: June 5, 2001
    Assignee: Denso Corporation
    Inventors: Shoji Miura, Satoshi Shiraki, Tetsuaki Kamiya, Makio Iida
  • Patent number: 6236064
    Abstract: A liquid-crystal electro-optical device capable of compensating for the operation of any malfunctioning one of TFTs (thin-film transistors) existing within the device if such a malfunction occurs. Plural complementary TFT configurations are provided per pixel electrode. Each complementary TFT configuration consists of at least one p-channel TFT and at least one n-channel TFT. The input and output terminals of the plural complementary TFT configurations are connected in series. One of the input and output terminals is connected to the pixel electrode, while the other is connected to a first signal line. All the gate electrodes of the p-channel and n-channel TFTs included in said plural complementary TFT configurations are connected to a second signal line.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: May 22, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Mase, Masaaki Hiroki
  • Patent number: 6229216
    Abstract: An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon substrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: May 8, 2001
    Assignee: Intel Corporation
    Inventors: Qing Ma, Harry Fujimoto
  • Patent number: 6229222
    Abstract: Second electrode pads are formed in a circuit forming region in a surface of a semiconductor chip so as to be electrically connected to first electrode pads formed in an electrode pad region, respectively. The surface of the semiconductor chip is coated with a sealing resin layer and second bumps are formed on the surface of the sealing resin layer so as to be electrically connected to the second electrode pads, respectively.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: May 8, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shinji Ohuchi
  • Patent number: 6225676
    Abstract: A semiconductor device having multiple circuit elements capable of performing different functions and that operate at a high frequency includes island regions on which the circuit elements are located and isolation regions that surround the island regions and thus, the circuit elements. The island regions electrically separate the circuit elements from each other. A capacitor is connected between a substrate portion of the semiconductor device and ground. The isolation regions include a conductive region with a conductivity type opposite to the conductivity type of the substrate portion, such that a parasitic capacitor is formed between the substrate portion and the conductive region. The parasitic capacitor prevents signal leakage between the circuit elements and the island regions.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: May 1, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshinobu Hattori, Masahiro Tsukahara, Shinji Saito
  • Patent number: 6222272
    Abstract: In a film carrier with a conductive circuit formed, an opening is formed in a particular position relative to where the conductive path is to be formed. The opening is a through-hole, filled with a conductive material to form a conductive path. The conductive circuit has a concave face, provided according to certain formulae. The film carrier can cope with a fine-pitched and highly dense mounting, while prohibiting pulling out of the conductive path by an external force. The film carrier does not suffer from fallout of the conductive path, and has increased electrical connection reliability.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: April 24, 2001
    Assignee: Nitto Denko Corporation
    Inventors: Yoshinari Takayama, Kazuo Ouchi, Atsushi Hino
  • Patent number: 6218723
    Abstract: A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: April 17, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Delpech, Etienne Robilliart, Didier Dutartre
  • Patent number: 6218698
    Abstract: A new capacitor structure of a Flash memory (Flash) cells on a supporting substrate's existing topography, including existing topography provided by adjacent word lines is provided. The gate of the Flash memory cell is constructed as an integral part of the new capacitor cell structure. An increased capacitive coupling ratio is achieved whereby reduced programming voltage is required while yielding more a more compact memory cell structure. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.
    Type: Grant
    Filed: August 17, 1998
    Date of Patent: April 17, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Tran T. Hai
  • Patent number: 6218699
    Abstract: The component has a channel zone and an oppositely doped zone in a semiconductor substrate. The channel zone and a peripheral region of the first doped zone are separated by a gate dielectric from an overlying channel gate electrode. The first doped zone is predominantly separated by a tunnel dielectric from an overlying tunnel gate electrode. When a suitable voltage is applied to the first doped zone, the tunnel current from the tunnel gate electrode generates an avalanche breakdown in the semiconductor substrate. A current results between the terminals of the channel zone and the first doped zones that is amplified by several orders of magnitude.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: April 17, 2001
    Assignee: Infineon Technologies AG
    Inventor: Ronald Kakoschke
  • Patent number: 6215185
    Abstract: An object is to obtain long-term reliability of an electric connection in a power semiconductor module. In a power semiconductor module, the main circuit interconnection directly connected to a power semiconductor chip (3) is formed of a busbar (6) and the power semiconductor chip (3) and the busbar electrode (6a) of the busbar (6) are electrically connected through a conductive resin (12). A member (13) having lower thermal expansion than the busbar electrode (6a) is joined to the busbar electrode (6a) in the part adjacent to said power semiconductor chip (3).
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: April 10, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Kikuchi, Hirofumi Fujioka, Toshiyuki Kikunaga, Hirotaka Muto, Shinichi Kinouchi, Osamu Usui, Takeshi Ohi
  • Patent number: 6208008
    Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kenneth C. Arndt, Richard A. Conti, David M. Dobuzinsky, Laertis Economikos, Jeffrey P. Gambino, Peter D. Hoh, Chandrasekhar Narayan
  • Patent number: 6207987
    Abstract: On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: March 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Isao Tottori
  • Patent number: 6204555
    Abstract: The microwave hybrid integrated circuit, is providing having a dielectric board (1) provided with a topological metallization pattern (2) and a number of recesses (3) in which semiconductor chips (5) are fixed with a binder (4). The face surface of the chips (5) provided with contact pads (6) are coplanar with the surface of the board (1), and the contact pads (6) of the chips (5) are electrically connected to the topological metallization pattern (2). The walls of the recesses (3) are inclined towards the plane of the board (1) at an angle (&agr;) of 90.1 to 150°.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: March 20, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Viktor Anatolievich Iovdalsky