Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

Abstract: A semiconductor device is formed in a self-light-emitting apparatus having a substrate and a plurality of self-light-emitting elements formed on the substrate. The semiconductor device is used to drive one of the self-light-emitting elements. The semiconductor device includes an active layer of semiconductor material, in which a source region and a drain region are formed. A source electrode has a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance. The source electrode is electrically coupled to the source region. A drain electrode has a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance. The drain electrode is electrically coupled to the drain region. An insulation layer is formed on the active layer. A gate electrode is formed on the insulation layer.

Abstract: A fabrication process and transistor are described in which a transistor having a diffusion barrier located in the bottom layer of a stacked (i.e., multi-layer) gate conductor is formed, thereby reducing the diffusion of dopants from the gate conductor to the underlying channel region. In a general embodiment, multiple gate conductor layers are formed and arranged in a vertical stack, and a diffusion barrier is introduced into one or more layers of the stack. In a preferred dual-layer embodiment, a first gate conductor layer (i.e., the bottom layer) having a first thickness is deposited upon a gate dielectric layer. An argon distribution is then introduced into the first gate conductor layer to form an argon diffusion barrier in the first gate conductor layer. A second gate conductor layer having a second thickness is then deposited upon the first gate conductor layer.

Abstract: The semiconductor device possesses a structure in which on one surface of a wiring substrate a semiconductor element is mounted with a face down and is electrically connected through bumps made of such as solder or the like. In a gap portion between the wiring substrate and the semiconductor element, a resin encapsulation layer (underfill) of epoxy resin or the like is filled to form, thereby alleviating stress due to difference of thermal expansion coefficients of the wiring substrate and the semiconductor element, and mechanically protecting connection portion. An average gap H between the semiconductor element and the wiring substrate, with an average pitch of bumps P and deviation of the gap D, satisfies the equationP/4-D/2.ltoreq.H.ltoreq.P/4+D/2.The semiconductor device is high in reliability of bonded portions and enables to finish filling procedure of resin material for forming underfill in a short time.

Abstract: A method of forming semiconductor devices in accordance with the present invention includes the steps of providing a deep trench in a substrate, the deep trench having a lower portion and forming a dielectric layer in the deep trench by lining the lower portion of the deep trench with a dielectric layer, the dielectric layer including titanium. A semiconductor device includes a substrate having a trench formed therein, a storage node formed in the trench and capacitively coupled to the substrate and a dielectric layer formed in the trench between the storage node and the substrate, the dielectric layer lining a lower portion of the trench wherein the dielectric layer includes titanium oxide.

Abstract: An array based application specific integrated circuit includes four application specific integrated circuits on one die. Each of the four application specific integrated circuits functions in a certain mode. Only one of the four application specific integrated circuits is activated at any time. Activation of a mode is determined by the configuration of mode selection circuitry of the array based application specific integrated circuit. The four modes are not interrelated, and the four application specific integrated circuits do not share transistors in the array based application specific integrated circuit. The four application specific integrated circuits may share input/output pins of the array based application specific integrated circuit.

Abstract: A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions.

Abstract: A semiconductor device and a method of manufacture therefor. The semiconductor device includes: (1) a substrate having a recess therein, (2) an aluminum-alloy layer located over at least a portion of the substrate and filling at least a portion of the recess and (3) a protective metal layer at least partially diffused in the aluminum-alloy layer, the metal protective layer having a high affinity for oxygen and acting as a sacrificial target for oxygen during a reflow of the aluminum-alloy layer.

Abstract: An object of the present invention is to provide a semiconductor device where a metal wiring pattern is improved in order to prevent photoresist foaming from occurring without employing a special process, even if a protective layer void occur in a wire to wire space in the metal wire, and an arrangement method for a semiconductor device pattern. To achieve the above object, the present invention provides a semiconductor device comprising a first wiring layer and a second wiring layer arranged in a row on a semiconductor substrate, and a insulating layer on the first wiring layer and the second wiring layer so that a first portion of the insulating layer on the first wiring layer is prevented from touching a second portion of the insulating layer on the second wiring layer.

Abstract: On a semiconductor substrate, a registration measurement mark and intended patterns monitored by the registration measurement mark are provided. Step or level difference between the surface of registration measurement mark and the surface of intended patterns is made to be within .+-.0.2 .mu.m. By such structure, it becomes possible to accurately monitor the intended patterns by utilizing the registration measurement mark.

Abstract: A semiconductor device according to the present invention is formed on a semiconductor chip and has a common module and a plurality of selectable modules. Each selectable module on the semiconductor chip performs a defined function and has a separate input power terminal. The device also has a voltage pad for connecting to a first voltage source having a first voltage level, so that the voltage pad supplies power to the input power terminal of each selectable module. The output of each selectable module may be connected to one common output pad, or alternatively, may be connected to a dedicated output pad. Also connected to each selectable module is a die/sort pad used for disconnecting a corresponding selectable module from the first voltage source. In the wiring between the first voltage source and the selectable modules, there is provided a plurality of fuses, each fuse having first and second terminals.

Abstract: Disclosed is a diode device in which two electrodes of regions forming both terminals are provided on the same face, thereby enabling the device to be connected to a circuit substrate by face-down bonding. Since a region is located within the semiconductor base, an electrode cannot be connected at the top face thereof; to overcome this, a groove is provided extending in a perpendicular direction from the top face of the semiconductor base to the region, and an electrode is provided in the groove. Then, the electrode in the groove is exposed at the top face, enabling the electrodes of both regions to be connected at the top face.

Abstract: Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations and the like, thereby improving reliability, and a method for controlling the semiconductor device.

Abstract: A fine wire is fabricated by supplying metal atoms to one row or a plurality of rows formed by extraction of terminated atoms or molecules to the surface of substance made non-conductive by terminating all dangling bonds on the surface thereof with atoms or molecules. The conductivity of the fine wire can be attained by supplying metal atoms larger in number to that required for just terminating dangling bonds formed by extraction of terminated atoms or molecules.

Abstract: The invention relates to a solder bump of an inhomogeneous material compoion for connecting contact pad metallizations of different electronic components or substrates in flip-chip technology, as well as to a method of making such a solder bump. A solder bump consists of a space defining high-melting solder bump core and a layer of a preferably low-melting solder material deposited thereon. The preconditions required for soldering, such as solder deposition, bump height and soldering temperature are thus all combined in the solder bump.

Abstract: The present invention provides a barium titanate-based semiconducting ceramic which exhibits excellent PTC characteristic and which can be fired at a temperature lower than 1000.degree. C. The present invention also provides an electronic element fabricated from the ceramic. The semiconducting ceramic contains, in a semiconducting sintered barium titanate; boron oxide; an oxide of at least one of barium, strontium, calcium, lead, yttrium and a rare earth element; and an optional oxide of at least one of titanium, tin, zirconium, niobium, tungsten and antimony in which the atomic boron is0.005.ltoreq.B/.beta..ltoreq.0.50 and1.0.ltoreq.B/(.alpha.-.beta.).ltoreq.4.0wherein .alpha. represents the total number of atoms of barium, strontium, calcium, lead, yttrium and rare earth element contained in the semiconducting ceramic, and .beta. represents the total number of atoms of titanium, tin, zirconium, niobium, tungsten and antimony contained in the semiconducting ceramic.

Abstract: In a semiconductor device in which a source and a drain are formed on both sides of a buried gate provided in a trench, metal wires for the source and the drain are provided above the source and drain, via an intervening interlayer insulation film, a wire for a gate being provided so as to be sandwiched between the source and drain wires, this being formed on the same level of interconnect layers as the source and drain wires and being formed over the gate.

Abstract: A stable low-connecting resistance connection arrangement having a high yield rate without using any special material or process for a substrate. A flip-chip connecting structure in which the semiconductor integrated circuit (IC) chip is mounted directly on an organic circuit substrate. To achieve reliable connection and low-connecting resistance, the present invention absorbs variation of the heights of projecting electrodes formed on a semiconductor IC chip and substrate electrodes of an organic circuit substrate for example, by deforming the substrate electrodes and/or substrate layer of the organic circuit substrate. Resin of a conductive paste disposed between the projecting electrodes and substrate electrodes is squeezed out leaving a high density conductive particle layer to lower a contact resistance between such electrodes.

Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.