Abstract: In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed.

Abstract: A semiconductor structure includes a semiconductor active region of a first conductivity type including a channel region and a non-channel region surrounding the channel region; an insulation film extending over at least the channel region; at least a control electrode on the insulation film for applying an electric field to the channel region; at least a first diffusion region of the first conductivity type occupying the channel region for defining a threshold voltage of the channel region; and at least an ion-implantation stopper film covering at least a part of the non-channel region but not covering at least a center region of the control electrode, and the ion-implantation stopper film being made of a material preventing ions from penetrating the ion-implantation stopper film in an ion-implantation for forming the first diffusion region.

Abstract: The microwave hybrid integrated circuit, is providing having a dielectric board (1) provided with a topological metallization pattern (2) and a number of recesses (3) in which semiconductor chips (5) are fixed with a binder (4). The face surface of the chips (5) provided with contact pads (6) are coplanar with the surface of the board (1), and the contact pads (6) of the chips (5) are electrically connected to the topological metallization pattern (2). The walls of the recesses (3) are inclined towards the plane of the board (1) at an angle (&agr;) of 90.1 to 150°.

Abstract: A SOI MOS field effect transistor includes: a superficial top semiconductor layer of a first conductivity type formed on a SOI substrate; source and drain regions of a second conductivity type arranged apart from each other on the top semiconductor layer; a P-type first channel region, an N+-type floating region, and a P-type second channel region formed in this order in a self-aligned manner and disposed between the N+-type source region and the N+-type drain region for an N-type MOSFET, or an N-type first channel region, a P+-type floating region, and an N-type second channel region formed in this order in a self-aligned manner and disposed between the P+-type source region and the P+-type drain region for a P-type MOSFET; and two gate electrodes for controlling the first and second channel regions, wherein a doping concentration of the second channel region adjacent to the drain region is lower than a doping concentration of the first channel region adjacent to the source regi

Abstract: First and second MOS transistor elements, each having two source pads respectively arranged in the vicinity of two opposite corners and a gate pad arranged in the vicinity of a corner between these two corners, and a light receiving element arranged on a second terminal. In this way, wires respectively connecting gate pads of the first and second MOS transistor elements and the light receiving element are shortened. A source pad of the first MOS transistor element adjacent to the second terminal and the second terminal can be connected by a wire, so this wire can be shortened. A source pad of the second MOS transistor element adjacent to the second terminal and the second terminal can be connected by a wire, so this wire also can be shortened.

Abstract: A semiconductor package and method for fabricating same is provided that includes a printed circuit board having an electrical circuit formed therein, a plurality of semiconductor chips vertically attached at fixed intervals to the printed circuit board and conductive connecting members that couple bonding pads on each semiconductor chip to pads on the printed circuit board. An encapsulation body encapsulates the semiconductor chips and the conductive connecting members above the printed circuit board. External connection terminals can be attached on a lower side of the printed circuit board for electrical connection to the semiconductor chips through the electrical circuit in the printed circuit board. The semiconductor package and method has increased mechanical and electrical reliability. The semiconductor package is preferably an ultra high density integrated circuit semiconductor package.

Abstract: An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.

Abstract: A semiconductor device excellent in bonding strength of bumps with respective protruded electrodes and having high reliability wherein a wiring pattern 28 to be connected to an electrode 22 of a semiconductor chip 20 is formed on an insulting film 23 formed on the semiconductor chip 20 in which the electrode 20 is formed, protruded electrodes 32 are formed on the wiring pattern 28, the wiring pattern 28 is covered with a protective film 36, and a bump 38 for external connection is formed on the end portion of each of the protruded electrodes 32 exposed from the protective film 36, the bump 38 is formed in such a manner that the bump is bonded to the at least entire end face of each of the protruded electrodes 32.

Abstract: A photodiode is provided comprising a substrate, a well with a first electric type within the substrate, a heavily doped region with a second electric type within the well, and a insulating layer on the substrate. The insulating layer in the position on the heavily doped region is thinner than in other positions. A junction is thus formed between the heavily doped region and the well.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate. A semiconductor film pattern is formed on the insulating film. A direct thermal nitriding method is performed to at least a portion of the semiconductor film pattern. The direct thermal nitriding method is performed by lamp annealing in a gas composed of nitrogen such that a thermally nitrided film has a film thickness of equal to or thicker than 1.5 nm. Thus, invasion of a hydrogen atom or ion into the semiconductor film pattern can be prevented.

Abstract: Obtained are a semiconductor device which can be implemented with high density of integration while ensuring a constant capacitor capacitance in high reliability and a method of fabricating the same. The semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and an electrode formed on the first insulating film. The first insulating film contains a halogen element and a combination of silicon and nitrogen or a combination of silicon, oxygen, and nitrogen. The maximum concentration of the halogen element in the first insulating film ranges from 1020 atoms/cm3 to 1021 atoms/cm3 inclusive. With this structure, the dielectric breakdown strength and the like of the insulating film increase, and the reliability of the insulating film improves.

Abstract: A semiconductor device having a conductive layer of small conductive resistance and including only a small step is provided. The semiconductor device comprises a first source line extending in one direction and a silicon oxide film having a contact trench reaching the first source line. The contact trench extends in one direction along the first source line. The semiconductor device further comprises a second source line which is formed in the contact trench. A part of the second source line exposes a partial surface of the first source line to be in contact with this partial surface of the first source line.

Abstract: Electrostatic discharge protection for analog switches using silicon-controlled rectifiers. Two silicon-controlled rectifiers (SCRs) may be formed in a common isolation region of an integrated circuit. Each SCR has its gate and cathode coupled together so as to be self triggering. The SCRs are connected in parallel in reverse polarity and coupled between the analog switch input or output and ground. In normal switch operation, both SCRs will be off, though when the voltage of the protected switch connection exceed on of the supply rails, one of the SCRs will trigger, providing a low impedance connection to ground. Once the voltage returns to normal, the SCR will automatically release.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A structure and method are provided for designing the architecture of a routing structure in a programmable logic device that maximizes the number of possible paths for an available diffusion area. The method comprises steps for selecting wire directions for a plurality of wires interconnectible at a unitary diffusion area of an integrated circuit device or portion thereof. The steps of the inventive method result in a highly alternated array of wire directions, including serial sets of four wires composed of four wires extending in four compass directions. In one embodiment of the inventive method, the first two wire directions are repeated from set to set, while the second two wire directions are alternated. A second embodiment with a repeating pattern of 24 wire directions is also disclosed.

Abstract: Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers.

Abstract: A method and apparatus for controlling the growth of an oxide, such as a gate oxide, in a semiconductor device manufacturing process takes into consideration the ambient atmospheric pressure in order to reduce the variance in gate oxide thicknesses between wafer lots. The pressure in the oxide diffusion tube is maintained at a constant pressure near the ambient atmospheric pressure during the oxide diffusion process. Alternatively, the furnace time is changed from lot to lot as a function of changes in the ambient atmospheric pressure in order to maintain the gate oxide thickness at a constant value between wafer lots.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.