Patents Examined by David L. Robertson
  • Patent number: 7707376
    Abstract: An information processing apparatus including: a nonvolatile memory; a volatile system memory in which predetermined data stored in the nonvolatile memory is developed; a control section to save the predetermined data stored in the system memory in the nonvolatile memory when a start of power-off operation is detected; and a storage section that stores a first timing information representing a time point of terminating the operation of saving the predetermined data in the nonvolatile memory, and a second timing information representing a power-off time point, wherein the control section compares the first timing information stored in the storage section with the second timing information, subsequent to the next operation of turning on of the power.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: April 27, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Tomoya Ogawa, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Patent number: 7580759
    Abstract: Systems and methods are provided for burnishing a recording head in-situ in a magnetic recording disk drive. The burnishing process generates a tribocurrent, which is electricity generated by the rubbing of dissimilar materials. Different materials exhibit widely different tribocurrent characteristics while in sliding contact. The tribocurrent thus acts as an indicator of the particular materials of the recording head making contact with the magnetic recording media during different stages of the burnishing process. The tribocurrent is thus monitored to determine when it reaches a threshold value. The threshold value indicates that the burnishing has exposed a particular material of the recording head. Thus, the burnishing process may be stopped upon the tribocurrent reaching the threshold value so that the read sensor of the recording head is not burnished and inadvertently damaged.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: August 25, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Bruno Marchon, Charles M. Mate, Bernhard E. Knigge, Kurt Rubin
  • Patent number: 7165142
    Abstract: A data storage array linking operation switching control system is proposed, which is designed for use in conjunction with an array-type data storage device that is composed of a plurality of data storage unit and associated with at least two data access channels, with the capability of selectively switching the linking between the data storage units and the data access channels for the purpose of providing various linking modes of different utilization objectives with hot spare capability, including a backup linking mode, a partitioned linking mode, and a high-performance linking mode. This capability allows the array-type data storage device to be set to different linking modes based on different utilization objectives, which allows the system management of network servers to be more flexible in application.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: January 16, 2007
    Assignee: Inventec Corporation
    Inventors: Chun-Liang Lee, Chih-Hung Kuo
  • Patent number: 7146459
    Abstract: A method of writing data to a disk, said method performing a write-modify-read for every partial 8 byte write, said method comprising: receiving a request for a sequence of L bytes; determining whether the last byte of the sequence of L bytes is last byte of an 8 byte boundary in a sector of the disk; modifying, if the last byte of the sequence of L bytes is not the last byte of an 8 byte boundary in a sector of the disk, the number of bytes L by an amount of bytes that would allow the last byte of reduced request to be the last byte of an 8 byte boundary in a sector of the disk, said modified number of bytes represented by M; requesting a sequence of M bytes receiving the sequence of M bytes; writing the sequence of M bytes to one or more disk sectors with continuous write steps whereby the sequence of M bytes does not need a partial 8 byte write and there is no read-modify-write step.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventor: Kelvin Wong
  • Patent number: 6961838
    Abstract: The present invention provides a method for copying data through a virtualized storage system using distributed table driven (I/O) mapping. In a system having a virtual disk (the “original disk”), a persistent mapping table for this virtual disk exists on a controller, and volatile copies of some or all entries in this mapping table are distributed to one or more more mapping agents. The method of the present invention creates a new virtual disk mapping table that has the exact same entries as the mapping table as the original virtual disk. The new snapshot disk then shares the same storage as the original disk, so it is space efficient. Furthermore, creating new snapshot disk involves only copying the contents of the mapping table, not moving data, so the creation is fast. In order to allow multiple virtual disks to share storage segments, writes to either the original virtual disk or the snapshot copy cannot be seen by the other.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: November 1, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James M. Reuter, David W. Thiel, Richard F. Wrenn, Robert G. Bean
  • Patent number: 6925485
    Abstract: The present invention is directed to a proxy cache preloader. According to an embodiment of the present invention, a Hyper Text Transfer Protocol (HTTP) client intermediary having a proxy cache is used to provide multiple client computing devices with access to Internet data in the cache. When a device needs access to Internet data (i.e., a web page), a preloader/refresh mechanism is employed which uses a preloader algorithm. In one embodiment, the preloader algorithm checks to see if the current request is for an HTTP Uniform Resource Locator (URL). If not, the data is re-loaded into the proxy cache. If the current request is a request for HTTP, the preloader mechanism determines if optimization is enabled for the URL. If not, the data is re-loaded into the proxy cache. Otherwise, an information retrieval method (e.g., an HTTP GET) optimization algorithm is employed.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: August 2, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Feng Wang, Jay Brandenburg, Ronan French, David C. Tracey
  • Patent number: 6907493
    Abstract: An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based memory system, and a non-packet based memory system. Communications from a memory controller, intended to directly communicate with a RAMBUS RDRAM memory system, are translated for a memory system which does not comprise RAMBUS RDRAM. The interface device, or integrated circuit, is not located with the memory system. That is, the memory modules do not include the interface circuit. Instead, the interface device is located with the processor motherboard, or with the controller/bridge integrated circuit chip set, such that it is electrically located between a controller and main memory sockets.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 14, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Ryan
  • Patent number: 6892279
    Abstract: A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main memory are accessed simultaneously. If the buffer contains the address requested, the buffer immediately begins to provide the associated row head data in a burst to the cache memory. Meanwhile, the same row address is activated in the main memory bank corresponding to the requested address found in the buffer. After the buffer provides the row head data, the remainder of the burst of requested data is provided by the main memory to the CPU.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 10, 2005
    Assignee: MOSAID Technologies Incorporated
    Inventor: Nagi Nassief Mekhiel
  • Patent number: 6889284
    Abstract: A memory translation hub comprising a memory channel interface, a memory bus interface, and a command generator coupled to the memory channel interface and to the memory bus interface. The memory channel interface receives a memory control packet from a memory channel. The memory bus interface provides a memory bus. The command generator causes the memory bus interface to provide memory control signals on the memory bus responsive to the memory control packet.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: May 3, 2005
    Assignee: Intel Corporation
    Inventors: Puthiya K. Nizar, Khong S. Foo
  • Patent number: 6880045
    Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: April 12, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Fong Pong, Lance Russell, Tung Nguyen
  • Patent number: 6868477
    Abstract: A skip mask mechanism is implemented in a disc drive in order to increase performance by minimizing the number of necessary disc rotations required while executing a set of pseudo-sequential commands. The drive includes an interface between the host computer and the drive, a read/write channel between the interface and the transducer/head, a formatter between the interface and the read/write channel for timing when data is transferred between the interface and the read/write channel, and a skip mask mechanism interposed between a target calculator and the formatter that provides a masked input to the formatter for controlling passage of data between the interface and the read/write channel.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: March 15, 2005
    Assignee: Seagate Technology LLC
    Inventors: Edward Sean Hoskins, Francis T. Seuberling
  • Patent number: 6851027
    Abstract: In a memory management system, a memory is organized into blocks, each block having one of a plurality of predetermined block sizes. When a new data chunk of data is received by the memory management system, portions of the data chunk may be stored in blocks of the large block type until the remainder of the data chunk is less than the large block size. Thereafter, the remainder of the data chunk may be stored in another large block or a plurality of smaller blocks, depending upon its size.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: February 1, 2005
    Assignee: Intel Corporation
    Inventor: Johannes K. Hansen
  • Patent number: 6850969
    Abstract: A method for storage and retrieval of information includes coupling a plurality of clients to communicate with a storage device via a network, and reading out data from a selected location on the storage device to a memory of one of the clients. After the client has modified the data in the memory, the storage device determines whether the modified data can be written back to the selected location as part of an atomic operation together with the reading out and modifying of the data. The modified data is stored in the selected location only after verifying that the modified data can be written back to the selected location as part of the atomic operation.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: February 1, 2005
    Assignee: International Business Machined Corporation
    Inventors: Edya Ladan-Mozes, Dan Touitou, Ohad Rodeh
  • Patent number: 6845438
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Patent number: 6813688
    Abstract: A system may include mirroring logic, a controller, and first and second devices (e.g., data storage devices). The first and second devices may include multiple registers. The mirroring logic may be configured in a first mode wherein the mirroring logic allows the registers of the first device to be accessed from the controller and prevents the registers of the second device from being accessed from the controller. The mirroring logic may be configured in a second mode wherein the mirroring logic allows the registers of the second device to be accessed from the controller and prevents the registers of the first device from being accessed. The first and second devices may be configured via the mirroring logic such that the first and second devices are selected simultaneously. When selected simultaneously, the first and second devices may carry out a subsequently issued command substantially simultaneously.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: November 2, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Chia Y. Wu, Whay S. Lee, Nisha D. Talagala
  • Patent number: 6785767
    Abstract: A mass storage system. Two or more dissimilar non-volatile storage mediums have the appearance to an operating system of a single device. In an embodiment, the storage mediums are located within a hard disk drive. In a further embodiment, the non-volatile storage medium is block oriented.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventor: Richard L. Coulson
  • Patent number: 6766409
    Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: July 20, 2004
    Assignee: Fujitsu Limited
    Inventors: Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh, Masaru Takehara
  • Patent number: 6760826
    Abstract: A method for managing a memory of a computer system to store a data of a first size, comprising the steps of defining chunks of the memory, wherein each chunk is a continuous memory space of a predetermined size. Defining chunk pools for managing the chunks, wherein each chunk pool corresponds to chunks of a particular size and defining unit pools for managing units of the first size, wherein the chunk pool corresponding to the unit pool provides a chunk of the particular size to be separated into the units of the first size, and the data of the first size is stored in the units.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: July 6, 2004
    Assignee: Wind River Systems, Inc.
    Inventors: Kadir Ozdemir, Shankar Jayaraman
  • Patent number: 6751160
    Abstract: A memory control apparatus which can effect memory high speed when performing a burst access from a CPU or the like to a memory is provided. When the access from the CPU is started, lower digits of the first address of the burst access are set into a counter. The CPU updates the data at a reading timing. By using the counter, the memory executes the access and the data obtained is stored into a latch. With this method, the data is read out from the memory earlier than conventionally, access can be executed at a high speed.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: June 15, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masahiko Murata
  • Patent number: 6748493
    Abstract: A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: June 8, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ronald Xavier Arroyo, William E. Burky, Jody Bern Joyner