Abstract: A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data.

Abstract: An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based memory system, and a non-packet based memory system. Communications from a memory controller, intended to directly communicate with a RAMBUS RDRAM memory system, are translated for a memory system which does not comprise RAMBUS RDRAM. The interface device, or integrated circuit, is not located with the memory system. That is, the memory modules do not include the interface circuit. Instead, the interface device is located with the processor motherboard, or with the controller/bridge integrated circuit chip set, such that it is electrically located between a controller and main memory sockets.

Abstract: There is provided a microcomputer including: an external apparatus discrimination means for discriminating that an external apparatus is connected to said microcomputer via an IC card interface section, based on a discrimination signal to be transmitted by said external apparatus, when the external apparatus is placed in a communicatable status which allows communication by feeding a power supply, a clock signal and initializing an operation; and memory contents change means for receiving data including a CPU program, from the external apparatus and executing changing of the contents of a memory, thereby allowing modification of a CPU program stored in the microcomputer during manufacture.

Abstract: An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each of the N ways comprising a data array capable of storing L cache lines and a tag array capable of storing L address tags, each of the L address tags associated with one of the L cache lines; and 2) address decoding circuitry capable of receiving an incoming memory address and accessing a target cache line corresponding to the incoming memory address only in a most recently used one of the N ways.

Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

Abstract: A secure write blocking circuit and method of operation thereof. The secure write blocking circuit includes enable and disable block input terminals coupled to a blocking circuit. The blocking circuit, such as a set/reset latch in a preferred embodiment, generates a block signal to prevent write access to a nonvolatile memory device, such as flash memory, in response to signals provided to the enable and disable input terminals. The secure write blocking circuit also includes an interrupt generator, coupled to the disable block input terminal, that generates an interrupt signal in response to a signal at the disable input terminal. In a related embodiment the secure write blocking circuit also includes a logic circuit, coupled to the blocking circuit, that receives the block signal and a write enable signal and in response thereto generates a control signal to a write enable input of the nonvolatile memory device.

Abstract: New techniques for generating entries in a content addressable memory (CAM) capable of comparison operations such as “greater than” and “less than” decisions are described. The techniques can be used with binary or ternary CAMs. The number of CAM entries needed to implement such decisions is drastically reduced for both binary and ternary CAMs. In the case of binary CAMs, one or multiple searches are needed to perform the comparisons, while in the case of ternary CAMs a tradeoff between the number of CAM entries and the number of searches can be found. As an example, a method of classifying data networking packets is implemented using the new techniques. A packet classifier based on subfields of a packet header is also described.

Abstract: A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is disclosed. A priority encoder having blocks of multiple match resolver circuits arranged in a logical order of priority receives a plurality of active matchline sense output signals. Each block of multiple match resolver circuits generates a flag signal and a local address corresponding to the highest priority active matchline sense output signal received. Control logic receives flag signals from the multiple match resolver circuits, and identifies the highest priority multiple match resolver circuit that has received an active matchline sense output signal. The control logic then disables all lower priority multiple match resolver circuits such that only the local address generated by the highest priority multiple match resolver circuit is passed by the priority encoder.

Abstract: A controller writes, after writing data into a nonvolatile memory unit, new management information that reflects the data wiring, into an area of the memory unit other than an area of the nonvolatile memory unit, which stores last management information. After that, the controller writes an old management information flag in relation to the last management information. Further, the controller searches the memory unit for updated, normal management information when initializing the memory system. If it does not find updated, normal management information, the controller restores updated management information on the basis of normal old management information related to the old management information flag.

Abstract: A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Abstract: A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.

Abstract: A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.

Abstract: A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.

Abstract: A computer system includes a memory controller that controls and formats transactions with a high speed memory. The memory controller includes a read queue, a write queue, and various other queues in which memory transactions may be stored pending execution. The memory controller periodically executes calibration cycles, such as temperature calibration cycles to the memory to reduce memory errors. The temperature calibration cycles may include an idle state during which no read transactions can be executed. The memory controller includes arbitration logic that reduces latency by issuing read transaction first. Once reads have been issued, the arbitration logic executes any pending temperature cycles. During the idle period of the calibration cycle, the arbitration logic schedules write transactions, and transactions to memory from other queues and devices, including precharge transactions, row activate transactions, refresh cycles, and other calibration cycles.

Abstract: In a disk array subsystem capable of changing the data redundancy method between a duplicating method and a parity method, the load of data transfer occurring at the time of changing the data redundant method is reduced. In the disk array subsystem, since one data of the duplicated data are used for data for the parity data area, the one data secures an area for storing parity prepared from the data. With the arrangement, it is not necessary to transfer the data when the data redundancy method is changed from the duplicating to the parity method and the data transfer load is mitigated.

Abstract: A hardware based modulo addressing scheme is described that is fast and makes efficient use of logic. The scheme uses a subtractor, multiplexers and AND/OR logic to produce modulo addresses to address, for example, a circular buffer in a memory. The buffer is defined by the user based on start and end addresses and an offset value. The offset may be positive or negative and may be greater than one.

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

Abstract: A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main memory are accessed simultaneously. If the buffer contains the address requested, the buffer immediately begins to provide the associated row head data in a burst to the cache memory. Meanwhile, the same row address is activated in the main memory bank corresponding to the requested address found in the buffer. After the buffer provides the row head data, the remainder of the burst of requested data is provided by the main memory to the CPU.

Abstract: An acquisition/playback device and a memory device including a solid-state write-once memory array are used to acquire and display digital information such as digital images, voice, music, or the like. Prior to display or other presentation, the digital information is stored in a re-writable memory. After the digital information has been displayed or otherwise presented to the user for review, the user then elects whether to store the digital information in the write-once memory array. Depending upon the user election, the digital information is either stored in the write-once memory array, or erased from the re-writable memory without being stored in the write-once memory array. In this way the limited storage capacity of the write-once memory array is preserved for digital information that is of long-term interest to the user.

Abstract: A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.