Abstract: A method of constructing firmware of a HDD which is capable of uploading code data written in a hard disk to a memory or downloading the code data from the memory to the hard disk. Codes needed to operate the HDD are stored in a prescribed area of a disk. A hard disk drive boot code and a servo core code are stored in a flash ROM of prescribed capacity. The codes stored in the disk is uploaded to a RAM of prescribed capacity by using the codes stored in the flash ROM, thus to implement the actual operation of the HDD.

Abstract: A binary-ternary configurable content addressable memory (CAM) (100). A plurality of CAM cells (114) including comparator logic cells (116) and paired storage locations (118, 118a, 118b) are directed by a signal at a mode terminal (120) to compare data provided at an input bus (110), either in binary mode against pre-stored content data or in ternary mode against pre-stored content and mask data. The comparator logic cells (116) generate respective bit signals (122) based on such comparison, and in this manner the plurality of CAM cells (114) may collectively be part of a CAM array block (104), which may optionally in turn work with a match detection block (106) to generate a match signal (126), and which may optionally in turn work with a priority encoder block (108) to generate a result signal at a result output (112).

Abstract: When a processing unit clock cycle period decreases (i.e., the processing unit operating frequency increases) such that the processing unit has only sufficient time to transfer accurately instruction fields from the instruction cache unit, the processing unit does not have sufficient time to determine the address of the next instruction to be retrieved from the instruction cache unit. In order to provide instruction fields to a pipelined processing unit with few breaks in the instruction field stream, the field in the program counter is incremented during to provide a speculative address of a next instruction field during a first clock cycle. During the first clock cycle, the instruction field identified by program counter field is accessed and transferred to the processor. The instruction field helps to determine an actual address of the next instruction field.

Abstract: A method for implementing a CAM function using a dual-port RAM. Data is stored in the memory array of the dual-port RAM as decoded “one hot” data words such that each data word is stored in one column, and each data word includes only one logic “1” bit value. Data match operations are then performed by reading a row of memory cells of the memory array in response to a match data word. If the row contains one or more of the logic “1” bit values, then the match data word matches (is equal to) one or more of the decoded “one hot” data words. One input port of the dual-port RAM is configured to automatically write decoded “one hot” data words into the memory array by accessing a selected memory cell in response to an X+Y-bit word. The encoded X+Y-bit word is transmitted to an address terminal of the first input port, and a logic “1” bit value is transmitted to a data input terminal of the first data port.

Abstract: An effectively “conditional”, cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU position information for cache lines corresponding to the cast out victim within snoopers and vertically in-line storage. The combined response logic may also receive information regarding the presence of shared or invalid cache lines in snoopers or lower level storage within the congruence class for the victim, or information regarding the read-once nature of the data access target. Based on these responses, the combined response logic determines whether the cast out should be cancelled and, if so, selects and drives the appropriate combined response code.

Abstract: Disclosed is a method, system, program, and memory for erasing data. A table is provided indicating different groupings of system functions. Each grouping indicates at least one system function. For each grouping there is code to perform erase operations. An erase command to erase data in at least one storage location is received. A determination is then made of the grouping having system functions supported by the system and the table is processed to determine the code for the determined grouping. The code for the determined grouping is executed to perform erase operations with respect to each storage location.

Abstract: A method, system, and computer program product are disclosed for determining the address type of a serial EEPROM in an electronic system. The method includes reading data from at least one location of the EEPROM for a first time and saving the data for future reference. Thereafter, a sequence of transactions is executed that alters the contents of the EEPROM in a prescribed manner if the EEPROM is of a first type. The sequence of transaction leaves the EEPROM in an unaltered state if the EEPROM is of a second type. Data is then read from at least one location of the EEPROM for a second time. The location of the data read from the EEPROM the second time is the same as the location of the data read the first time if the EEPROM is of the first type. The data read the first time and the data read the second time are then compared.

Abstract: A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.

Abstract: A cache memory system including a cache memory suitable for coupling to a load/store unit of a CPU, a buffer unit comprised of a plurality of entries each including a data buffer and a corresponding address tag. The system is configured to initiate a data fetch transaction in response to a first store operation that misses in both the cache memory and the buffer unit, to allocate a first entry in the buffer unit, and to write the first store operation's data in the first entry's data buffer. The system is adapted to write data from at least one subsequent store operation into the first entry's data buffer if the subsequent store operation misses in the cache but hits in the first entry of the buffer unit prior to completion of the data fetch transaction. In this manner, the first entry's data buffer includes a composite of the first and subsequent store operations' data.

Abstract: A high-performance dual-ported shared memory that interconnects two 32-bit PCI buses with a RAM memory that provides an address space of 64-bit words. The high-performance dual-ported shared memory provides two independent channels for reading from, and writing to, the RAM memory. By interleaving 64-bit read and write operations directed to the RAM memory with 32-bit PCI bus data transfer operations, and by internally buffering data, the high-performance dual-ported shared memory can independently provide data access at PCI data transfer rates to both PCI buses without introducing wait states.

Abstract: A method of using a reduced number of page tag registers to track a state of physical pages in memory systems are is described. An incoming system address request is received that includes a requested bank number and a requested page number. A page register located in memory controller corresponding to the requested bank number is then located and the stored page address included in the located page register is then compared to the requested page address. The requested page in the memory bank corresponding to the requested bank number is then accessed when the stored page address matches the requested page address for the requested memory bank. The stored page using page address from the page register of the bank which number is given by random page register number generator is closed if the requested bank and stored page address do not match. However, a new page using the page address from the incoming system address is opened after which the requested bank is accessed.

Abstract: A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with entries in the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Abstract: Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy with a coherency state of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state information appended to the combined operation and the snoop responses, whether a coherency upgrade is possible. If so, the combined response logic selects a snooper storage device to upgrade the coherency state of a respective cache line corresponding to the victim, and appends an upgrade directive to the combined response.

Abstract: A computer system includes hardware for selectively disabling alteration of data residing on a mass storage device which is subject to remote access. In one embodiment, a hard disk drive is operated in a conventional manner including both read and write modes when the system is being operated in a non-secure mode of operation, such as when remote access is not allowed. In a secure mode of operation, a locally operated switch is used to disable writing to the hard disk drive to maintain data integrity on the drive. The system may also include first and second electrically isolated buses and corresponding processors. In this configuration, the hard disk drive may be selectively connected to the first bus and processor for the storage of data, or to the second bus and processor when in a secure mode to provide for read-only remote access to the information stored on the hard drive.

Abstract: A method for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request by a processor of a first node to invalidate a remote copy of a cache line also stored within its cache memory at substantially the same time when a processor of a second node is also requesting to invalidate said cache line, one of the two requests is allowed to complete. The allowed request is the first request to complete without retry at the point of coherency, typically the home node. Subsequently, the other one of the two requests is permitted to complete.

Abstract: It has been discovered that a method and system can be produced which will, among other things, provide data processing systems having memory controllers with the ability to look ahead and intelligently schedule accesses to system memory. A method and system which improve data processing system memory access. The method and system provide a first-stage origin-sensitive memory access request reordering device, and a second-stage destination-sensitive memory access request reordering device operably coupled to said first-stage origin-sensitive memory access request reordering device. The first-stage origin-sensitive memory access request reordering device receives memory access requests having associated origin information, and reorders the memory access requests based upon the associated origin information.

Abstract: A first device includes a processor, a first memory, and a memory manager. A second device includes a second memory and a first application program, and a third device includes a third memory and a second application program. The first application program is loaded into the first memory to be executed by the processor. Application program variables related to the first application are stored in the first memory. The second application program to be executed by the processor is loaded into the memory in at least a partially overlapping manner of the first application program. The creation of second application program variables related to the second application program in the first memory is in a region not occupied by the first application program. Alternatively, the first and second application programs may be in the same device and/or memory.

Abstract: Cache memory is managed to update the data stored in the cache regardless of whether the address being operated upon is designated as cache inhibited. In this way, the contents of the cache are coherent with main memory so that when the processor redesignates a noncacheable range of addresses to be cacheable, the cache does not need to be flushed. Read operations follow cache inhibit faithfully.

Abstract: An apparatus for adjusting a STORE instruction having memory hierarchy control bits is disclosed. A multiprocessor data processing system includes a multi-level memory hierarchy. The apparatus for adjusting control bits within an instruction to be utilized within the multi-level memory hierarchy comprises a performance monitor and a bit adjuster. The memory hierarchy control bits indicates a memory level within the multi-level memory hierarchy to which an updating operation should be applied. In response to the outputs from the performance monitor, the bit adjuster alters at least one of the memory hierarchy control bits within the instruction in order to achieve optimal performance for the updating operation.

Abstract: An optimizing compiler for generating STORE instructions having memory hierarchy control bits is disclosed. The compiler first converts a first STORE instruction to a second STORE instruction. The compiler then provides an operation code field within the second instruction for indicating an updating operation. The compiler further provides a vertical write-through level field within the second instruction for indicating a vertical memory level and a horizontal memory level within a multi-level memory hierarchy to which the updating operation should be applied.