Abstract: If a word line is selected by inputting an immediate value and base address, whose values are determined at different timings, to an adder, the access speed decreases due to the constraint of the base address whose value is determined at a later timing. According to this invention, decoding is performed by inputting only the immediate value whose value is determined earlier to an address decoder AD. Thereafter, a word line WL is selected by performing rotation using the base address whose value is determined at a later timing. This makes it possible to start decoding processing without waiting for the determination of the value of the base address and increase the overall access speed.

Abstract: A system implementing an execute-in-place (XIP) architecture is presented comprising a plurality of XIP regions. To facilitate execute-in-place functionality across the multiple XIP regions, a virtual address table (VAT) is generated to store pointers to the objects stored in the non-volatile memory hosting the multiple XIP regions.

Abstract: In a disk array subsystem capable of changing the data redundancy method between a duplicating method and a parity method, the load of data transfer occurring at the time of changing the data redundant method is reduced. In the disk array subsystem, since one data of the duplicated data are used for data for the parity data area, the one data secures an area for storing parity prepared from the data. With the arrangement, it is not necessary to transfer the data when the data redundancy method is changed from the duplicating to the parity method and the data transfer load is mitigated.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: A portion of a storage controller's cache memory is used as a virtual solid state disk storage device to improve overall storage subsystem performance. In a first embodiment, the virtual solid state disk storage device is a single virtual disk drive for storing controller based information. In the first embodiment, the virtual solid state disk is reserved for use by the controller. In a second embodiment, a hybrid virtual LUN is configured as one or more virtual solid state disks in conjunction with one or more physical disks and managed using RAID levels 1-6. Since the hybrid virtual LUN is in the cache memory of the controller, data access times are reduced and throughput is increased by reduction of the RAID write penalty. The hybrid virtual LUN provides write performance that is typical of RAID 0. In a third embodiment, a high-speed virtual LUN is configured as a plurality of virtual solid state disks and managed as an entire virtual RAID LUN.

Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to a control logic in a memory controller, that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles, or may throttle down the operating speed of the memory devices, or may place some or all of the memory devices in a low power mode until conditions improve. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices.

Abstract: A memory device is adapted for prefetching data. The memory device has a memory cell array, with local sense amplifiers for receiving data bits prefetched from the memory cell array. The memory device also includes a serializer, and data paths that connect the local sense amplifiers to the serializer. Crossover connections are interposed between stages of the data paths. These transfer data bits between the data paths. Preferably they do that as part of being gates between the stages, which are in turn controlled by a clock. This way ordering is distributed within the data paths, and thus does not limit how fast the clock may become. In addition, the space used remains at a fundamental minimum.

Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an additional cache state which specifically indicates that a processor has released its lock on a cache line after it has performed any necessary modifications.

Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.

Abstract: Whether or not a recording device has a buffer underrun prevention function is determined. When such a function is present, recording data is sent to the recording device without being stored in a host buffer memory provided at the host device.

Abstract: An method of arranging address decoders in an improved manner in an integrated circuit memory is discussed. In the integrated circuit memory the address lines extending from the address circuitry of the integrated circuit memory are connected to address decoders, each word line of the memory being connected to an address decoder. The address decoders are connected to the address lines in a certain combination such that only one of the address lines is connected to adjacent address decoders. When connected in this manner the average propagation delay of each address line is substantially uniform. By reducing the maximum propagation delay in comparison with previously known arrangements of address decoders the speed at which the memory can be operated is increased.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: A file system includes at least one non-volatile semiconductor memory device, the at least one non-volatile semiconductor memory device including a plurality of erasure blocks, each erasure block including a plurality of sectors. The file system includes: a file system memory section for storing block state information for each erasure block, the block state information representing one of a plurality of block states, and for storing sector state information for each sector, the sector state information representing one of a plurality of sector states; and a file system control section for, when accessing the at least one non-volatile semiconductor memory device, guaranteeing integrity of data already stored in the at least one non-volatile semiconductor memory device based on the block state information and on the sector state information in the file system memory section.

Abstract: A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.

Abstract: A method of invalidating shared cache lines such as on a sharing list by issuing an invalidate acknowledgement before actually invalidating a cache line. The method is useful in multiprocessor systems such as a distributed shared memory (DSM) or non-uniform memory access (NUMA) machines that include a number of interconnected processor nodes each having local memory and caches that store copies of the same data. In such a multiprocessor system using the Scalable Content Interface (SCI) protocol, an invalidate request is sent from the head node on the sharing list to a succeeding node on the list. In response to the invalidate request, the succeeding node issues an invalidate acknowledgement before the cache line is actually invalidated. After issuing the invalidate acknowledgement, the succeeding node initiates invalidation of the cache line. The invalidate acknowledgement can take the form of a response to the head node or a forwarding of the invalidate request to the next succeeding node on the list.

Abstract: Methods improve state information retention when selecting a not-recently-used element in an array of N elements. A first method comprises the steps of subdividing the array of N elements into K groups, selecting a group from among the K groups, selecting an element that is set to a not-recently-used state from the elements in the selected group, and marking the selected element as recently-used. If all the elements in the selected group are marked as recently-used, the method preferably marks all the elements in the selected group, except the selected element, as not-recently-used. Alternately, the method simply marks all the elements in the selected group when all the elements in the selected group are marked as recently-used. The method also preferably cycles through the groups so that a different group is selected each time.

Abstract: The meta-data pattern for records in an orphan track is not readily compressible into a form suitable for maintaining in memory. A method is provided for periodically attempting to compress meta-data from orphan tracks as newly compressible meta-data patterns are made available. The method includes specifying a compressed representation for a first meta-data pattern and determining a second meta-data pattern formed by the meta-data associated with the orphan track. If the second meta-data pattern is consistent with the first meta-data pattern, a compressed representation of the second meta-data pattern is generated and maintained in memory. In an optional feature, meta-data that could not be compressed is collected and periodically transmitted to a data-analysis node for analysis.

Abstract: Disclosed is a headerless hard drive system that includes a head-disk assembly, a servo control logic, and a format calculator. The head-disk assembly includes a set of recordable disks for storing data. Each recordable disk having a plurality of tracks with each track having a plurality of servo wedges for dividing the track into a plurality of data frames. In this arrangement, one data frame is associated with one servo wedge and the tracks do not contain any header information that uniquely identifies the data frames in the tracks. The servo control logic coupled to the head-disk assembly to process the servo wedges for generating a signal that identifies a servo wedge being processed on a track. The format calculator is configured to convert the signal that identifies the servo wedge being processed to an associated sector number on the track.

Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to control logic in a memory controller that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices. In addition, the memory controller also monitors the expected remaining life of the memory devices, and the number of errors occurring in the memory devices, and based on these parameters, may change the frequency of the calibration cycles.

Abstract: New techniques for generating entries in a content addressable memory (CAM) capable of comparison operations such as “greater than” and “less than” decisions are described. The techniques can be used with binary or ternary CAMs. The number of CAM entries needed to implement such decisions is drastically reduced for both binary and ternary CAMs. In the case of binary CAMs, one or multiple searches are needed to perform the comparisons, while in the case of ternary CAMs a tradeoff between the number of CAM entries and the number of searches can be found. As an example, a method of classifying data networking packets is implemented using the new techniques. A packet classifier based on subfields of a packet header is also described.