Abstract: A memory network for a time division system. In memory for each time slot are stored the addresses of the telephone lines using that time slot. A call is processed by transferring addresses and control between time slots associated with various call functions such as registering dial pulses (register), supervising local calls (link) or supervising trunk calls (trunk). The addresses are sequentially brought from memory in the respective intervals representing the time slots in which the addresses are stored and retained in those time slots or transferred. For each time slot in which an address transfer occurs, a record of a transfer having been made is retained temporarily for that time slot. Reference is made to that record before a new address is stored in memory to prevent inadvertant errors causing address changes in memory.

Abstract: TV low cost remote control system using a microprocessor decoder. Control data is transmitted in digitally encoded form and comprises blocks of eight bits of data separated by gaps in transmission of equivalent length. Each data block consists of a start bit followed by seven bits of data for channel identification. Data is presented to the microprocessor on one input line which it samples regularly as a part of its main keyboard scan routine and in response to a start bit checks the data bits and gaps to determine presence of a valid command. The remote control information is decoded directly by the microprocessor. Using seven identification bits, a channel capacity of 128 channels is possible.

Abstract: A data link is additionally provided in a digital channel bank type transmission system without displacing or degrading any present voice or signaling channel capacities. The additional data channel is obtained by "borrowing" a major portion of the signaling subframe channel. A transmit circuit (FIG. 3 and FIG. 8) serves to time division multiplex a data channel into the signaling subframe channel by transmitting the signaling framing pattern in an intermittent periodic manner with preselected data bits interposed therebetween (waveform TDATA of FIG. 5). At the remote receiving terminal, a subframe recovery circuit (FIG. 7) serves to recover the signaling framing pattern embedded in the multiplexed subframe channel. A receive circuit (FIG. 4) at the remote terminal is responsive to a signal from the subframe recovery circuit to separate out the data bits in the multiplexed subframe channel.

Abstract: The present invention relates to a device for transmitting stochastically coded information, comprising a digital multiplexer and demultiplexer connected by a series transmission line and each controlled by addressing means, the addressing means of the multiplexer and the addressing means of the demultiplexer themselves being controlled by a common random noise generator of probability equal to 0.5.

Abstract: A multipoint communication digital transmission system in which the main data transceiver of each multipoint communication can communicate simultaneously with a plurality of secondary transceivers and they can each, in turn, communicate with the main data transceiver. First, second and third multiplexer means are provided, each at its own characteristic sampling rate. Selective switching is provided. Corresponding first, second and third multiplexing means are also provided.

Abstract: The standard D3 signalling frame bit pattern of a T1-type PCM telephone system is modified to provide a pattern in which (4n-3) separate low-speed data channels can be transmitted in a superframe consisting of 12n frames of the PCN carrier (n being a positive integer), without requiring a separate synchronization detector for superframe synchronization. Simple self-synchronizing circuit means are further disclosed for multiplexing a large number of essentially steady-state signals onto the low-speed data channels, and for positively detecting the onset and cessation of each steady-state signal, independently of the onset and cessation of any other steady-state signal, once in each group of k superframes, where k-1 is the number of steady-state signals being multiplexed.

Abstract: The subject of this disclosure is a Finite State Automaton (FSA) used as part of a term detector employed in a digital pattern search system (searcher). In particular the invention includes various advances in the art of FSA design which make the FSA practical for pattern recognition.Specifically, these advances minimize the amount of memory which is required in each FSA in performing pattern recognition, and allow a speed capability such that the searching can be performed at the rate at which a mass storage medium can supply data. The large amount of memory required and the low speed of processing in the prior state of the art made the use of an FSA impractical for most real applications.

Abstract: An arrangement for time-division multiplex data transmission having a data bus system which comprises a data bus circuit, several subscribers which are connected to the data bus circuit and have a transmitter part and a receiver part and communicate with one another by data transmission in a predetermined sequence in a given combination, and at least one clock generator, in which the sequence of all the given combinations of the subscribers runs through during a time frame and a time slot within the time frame is available for connecting each combination. Each subscriber includes at least one programmable counter for emitting a control signal when a programmed number has been reached and for resetting itself to zero when a given counting capacity which is the same for all counters has been reached. The programmable counter has a counter input connected to the clock generator and a first control output.

Abstract: An apparatus for reducing a sampling frequency which derives information with the bandwidth f.sub.B /N (N is an integer) having a sampling frequency of 2f.sub.B /N from an input FDM signal with a bandwidth up to f.sub.B having the sampling frequency 2f.sub.B has been found. The present apparatus comprises a pair of partial frequency reduction systems and a switch for alternately selecting the outputs of said partial frequency reduction systems to provide the output signal.

Abstract: Orthogonal-diphase coded digital signals are transferred in bursts on a transmission line. In order to facilitate synchronization of the signal receiver to the incoming signal bursts an extra pulse is added at the beginning of each transmitted burst, the polarity of this pulse being opposite to that of the following signal element. At the receiver this extra pulse is detected by comparison of the received signals with a threshold voltage and the next zero transition is then used as a basis for the synchronization. The threshold voltage will be self-adaptive if it is allowed to decrease exponentially with time from a start value corresponding to a short transmission line to a final value corresponding to a long transmission line. Furthermore, in order to eliminate DC residuals an extra pulse may be added at the end of each transmitted burst, the polarity of this pulse being opposite to that of the preceding signal element.

Abstract: Communication between a plurality of data stations (100(1)-100(N)) serially interconnected by way of a line (101) arranged in a ring is provided by bit interleaved data packets. A control station generates framing signals to designate the start of each packet, staggering the packets so that only one packet header appears on the line at a time. Processing equipment (114) at each station monitors all the headers, seizing "empty" packets if the station has a data burst to send and reading the data burst if the packet is addressed thereto.

Abstract: A directional coupler for duplex transmission for use with a transmitter/receiver unit is described. It includes a memory unit for providing a correction signal and a compensation circuit to which the correction signal is applied to supress that portion of the received signal which is derived from the transmitter. The memory unit is capable of storing values of the correction signal, the values being assigned to the different possible varients within a selected period of time, of time functions coming from the transmitter, and a decoder connected between the transmitter and the memory unit for detection of actual, transmitted signal variants. The decoder includes means for selection in the memory unit of the values of the correction signal assigned to the actual signal variants.

Abstract: Communication between a plurality of data terminals (101(1) to 101(b)) serially interconnected with a main terminal (102) is provided by data frames or packets having a data portion for accommodating a burst of data preceeded by a header portion for accommodating address data followed by an empty/full "flag" bit indicating whether the addressee station has withdrawn the data burst. If a terminal has a data burst to send, it locates an empty packet, inserts the addressee designation in the packet subsequent to any prior address that the packet might contain, interposes delay in the passage therethrough of the packet so that the duration is increased to accommodate the new address and overwrites the data burst into the data portion. The main terminal detects when the data burst is withdrawn and signals the originating terminal to remove the data delay.

Abstract: An apparatus for enabling communications between two or more transceivers when a plurality of transceivers share a common communication medium or channel. The geographical locations of the transceivers are such that the propagation delay between any source to destination pair is relatively a small function of the transmission duration or packet time. In order to prevent two or more transceivers from simultaneously transmitting over the common medium, each transceiver requires a control apparatus. The simultaneous transmission by two or more transceivers is not very likely due to different start times. However, if such start times differ by less than the propagation delay between the transceivers then interference will result. Hence the control apparatus includes a means of resolving such contention interferences by providing a retransmission delay to govern the transmission.

Abstract: The present invention provides a processor for interfacing a TDMA burst modem (40), which transmits and receives bursts of information at high data rates in assigned time slots, and slow speed terminal processing equipment. The present processor comprises circuitry (50) capable of detecting frame or superframe markers in a received sequence and regenerating such markers, after initiation, at the normal interval for such markers despite false alarms or missed marker signals. Other circuitry (53, 57 and 52, 62) causes a memory (48, 56) to directly output a burst of information during an assigned time slot to the modem (40) and directly store received information from modem (40) during a predetermined interval which is designed to start before and end after the expected arrival of an assigned burst. Slower processing equipment is then used to find and process the burst in the stored information.

Abstract: A duplex microwave radio communication and telemetry system for transmitting analog and digital data between fixed stations as well as to mobile stations wherein the microwave oscillator is stabilized by utilizing a free running oscillator which is controlled in frequency with the incoming modulation input and the output of the free running oscillator is supplied to a phase comparator and to a multiplier and the multiplier supplies an output to a mixer which also receives a portion of the input from the microwave oscillator and supplies an input to the phase comparator to provide a control signal for controlling the frequency of the microwave oscillator.

Abstract: A carrier terminal unit for interfacing 1.544 MHz PCM lines to a digital switch, wherein voice samples are switched at 2.048 MHz, provides bit synchronization, in-frame monitoring, delay equalization and correction, framing detection, and rate and format conversion. A common memory is utilized for the delay equalization and correction, framing detection and rate and format conversion functions. The memory acts as an elastic store for delay equalization. Delay correction is provided by monitoring the relative positions of the memory read and write addresses and initializing the write addresses after an overtaking of the read or write addresses by the other is detected. Rate and format conversion are provided by storing incoming PCM samples in the memory and reading the samples out in accordance with a predetermined sequence. Framing detection is provided by storing in memory every nth bit of three alternate frames of incoming data.

Abstract: Transmitting means for use in a serial type data transmission channel employing a plurality of coaxial lines for communicating digital data from the transmitting means to a receiving means. The transmitter means provides for transmission of data messages and message identifying data on a first coaxial line and the transmission of a clock on a second coaxial line. The transmitted clock is transmitted at a first repetition rate when a message is being transmitted and at a second repetition rate when message identifying data is being transmitted. The transmitting means employs shift register means capable of selectively shifting applied data in opposite directions so as to provide for the expeditious serial outputting of message and message identifying data to the first coaxial line during separate time periods.

Abstract: A control unit and a remote unit each including a transmitter and receiver with the remote unit transmitter and control unit receiver being synchronized first by means of a variable oscillator in the control unit and connected to the receiver in a closed loop, and the transmitter of the control unit and receiver of the remote unit being synchronized second by sensing errors between a received signal and the operating frequency of the receiver in the remote unit and transmitting the error signal back to the control unit by way of the previously synchronized transmitter/receiver for controlling the frequency of the transmitter in the control unit.

Abstract: Receiving means for use in a serial type data transmission system employing a plurality of coaxial lines. Digital data is transmitted to the receiving means in a manner such that one coaxial line contains data comprised of messages interposed with message identifying data, while another coaxial line contains a clock having one repetition rate when a message is being transmitted and another repetition rate when identifying data is being transmitted. The receiving means is optically coupled to these transmission lines and employs the received clock to generate strobe pulses having time spacings dependent on the clock repetition rate. These strobe pulses are in turn employed to extract the message and identifying data from the received signals, and to also provide indications of message availability.