Abstract: A time multiplex long distance transmission system for transmitting signals in both directions, particularly for street traffic signaling systems, utilizes a single timing generator which transmits a time slot pattern, preferably coded, to all stations by way of a few control channels, wherein existing information can be transmitted to the station by way of a respective further control channel for the station.

Abstract: A multi-rate TDMA communication system includes a baseline TDMA network and at least one auxiliary TDMA network oprating through the same satellite repeater. The baseline and auxiliary networks may each include a plurality of ground stations, the baseline network stations operating at a bit rate different from the bit rate of the auxiliary network. To maintain orderly communications, a station synchronized with the baseline frame reference burst (FRB) transmits a sub-frame reference burst (SFRB) which latter burst is at a bit rate common to the auxiliary network stations. The auxiliary network stations synchronize to the SFRB.

Abstract: An analog-signal gate circuit or sample-hold circuit is employed for processing a dot-sequential video signal derived from a solid state imaging device such as CCD imager. By changing a signal width, gain control operation is achieved, and phase shifting operation of the video signal is done by shifting an aperture center of the dot-sequential video signal. This system may be applied to a color signal conversion system wherein a dot-sequential color signal is converted directly to an NTSC color television signal. Further, white balance control for a solid state color television camera is another application of this system.

Abstract: A hybrid multiplexing method and communications system for controlling transmission of information between a plurality of remote terminals and a shared central facility over a common communications channel. The remote terminals are synchronously polled to ascertain whether or not the remote terminals desire access to the central facility. Asynchronous polling is utilized to establish communication between the central unit and the remote terminals desiring access to the central unit.

Abstract: A data communication system which includes a plurality of terminals and a data bus, wherein each of the terminals has autonomous access to the data bus. Normally, all terminals are enabled to receive messages on the data bus. To prevent the simultaneous transmission of messages by two or more terminals, each terminal continuously monitors the data bus and is enabled to transmit a message only when the data bus has been silent, e.g., there is an absence of messages on the data bus, for a predetermined period of time which is unique to the terminal, and when a periodic transmission interval for the terminal has been reinitiated. The periodic transmission interval is substantially the same for all terminals, and is measured at each terminal from the time of a previous message transmission thereby.

Abstract: The invention relates to a matrix wipe generator for television signals. With matrix switching, the television screen is divided into a plurality of blocks, and, if the screen originally contains the picture A, then picture B is switched into the blocks one at a time until all of the blocks, i.e., the whole screen, are filled with the picture B. The novel generator in accordance with the invention provides waveforms which give a Z-axis wipe effect, that is, the B picture appears to come into the screen from behind the A picture in each block.

Abstract: A time division multiplex (TDM) switching network having TDM switching units which, through time position conversion, selectively assign time slots on connected TDM lines is described. The TDM lines are formed into a matrix, the crosspoints of which are connected by the TDM aforementioned switching units. The TDM switching units have a fixed traffic capacity which is defined by the maximum number of time slot connections that the switching units are capable of making between the TDM lines connected thereto. The fixed traffic capacity of the switching units is dependent on the size of the TDM switching network but smaller than the maximum rated traffic capacity of the TDM lines. As a result, in the event the TDM switching network is expanded, the fixed traffic capacity of the additional TDM switching units can be progressively reduced.

Abstract: A digital multiplexing and demultiplexing system for time division multiplexing a number of incoming plesiosynchronous low rate component signals and a number of incoming plesiosynchronous intermediate rate component signals into an outgoing single high rate signal. A first multiplexing stage time stores and stuffs the low rate component signals and multiplexes them into synchronous intermediate rate signals. A second multiplexing stage stores and stuffs the plesiosynchronous and synchronous intermediate rate signals and multiplexes them into the outgoing high rate signal.

Abstract: A signalling arrangement for use in PCM systems includes a transfer control for determining whether signalling between exchanges should be transmitted over a speech channel or a signalling channel. If signalling is directed to information for setting up a call, a speech channel is used, whereas supervisory information employs a signalling channel. A marking memory is used having a memory cell per speech channel. A bit is stored in each memory cell for transfer of call set-up information.

Abstract: A multi-data recording system includes apparatus for generating two control signals of different frequency characteristics. A mixer is provided for interleaving the two types of signals. The display and recording of the data signals is accomplished under the control of the resulting composite signal from the mixer.

Abstract: Path test apparatus and a method for verifying the continuity of a data path in a telephone system between an input portion and an output portion of a telephone interface which receives and transmits telephone signals where the telephone system operates in time frames each consisting of a plurality of time slots. The apparatus includes a signal generator which connects a test signal to a selected time slot in said input portion. Means are provided for connecting a data path between a time slot in the input portion and a time slot in the output portion whereby the test signal occurs in the output portion. Means are provided for detecting the test signal in the output portion, thereby verifying the continuity of the data path.

Abstract: A bias boost circuit for a television receiver is disclosed, comprising a timing circuit for providing an exponentially decreasing bias to a video amplifier of the television receiver for a period of time corresponding to the initial warmup of the TV receiver, i.e. until the various amplifier and display portions are ready to display a high brightness image. The timing circuit comprises an RC circuit coupled to a power source of the TV receiver, whereby upon turn-on of the TV receiver the source's voltage is applied to the timing circuit, i.e. to its capacitor, to provide a decreasing voltage bias to the base of a transistor, whereby the transistor is gradually turned off thus decreasing exponentially a bias boost signal that is applied to the video amplifier and in particular, to its first stage.

Abstract: Analog image data pixels are sampled and held to produce a box car wave representative of the image data. Wave height differences are bridged by linear interpolation, with frequency enhancement imposed at the bridge junctures. The modified image wave is thresholded and sampled at a multiple of the original frequency to provide an image pixel stream comprised of both original image pixels having one or more interpolated image pixels therebetween.One or more intermediate image lines are interpolated by comparing binary image data, portions of which may be interpolated, on a pixel by pixel or multiple pixel basis one line pair at a time. The pixel comparison produces an address used to identify a specific image pixel pattern from multiple image pixel patterns stored in memory. The image pixel pattern taken from memory is used to form the interpolated intermediate line or lines.

Abstract: Disclosed is an analog multiplexer in which a plurality of emitter follower differential amplifiers formed of several pairs of bipolar transistors connected in parallel with each other are connected in common to one terminal of a power source through a current mirror load circuit, and to the other terminal of the power source via a switch circuit and a constant-current source. The switch circuit is to connect the constant-current source selectively to the common conjunction of the emitters of each pair of emitter follower differential amplifiers.

Abstract: Digital Carrier Trunks connected via a supervisory decoding and multiplexing logic to an electronic digital PABX. The circuit is arranged to receive or transmit the supervisory signal in either the "Ground Start", E&M modes or a combination of both in either the D2 or D3 signalling format over a T1 carrier span without converting to the analog signal form.

Abstract: A method of receiving a codirectional interface digital signal coded in bipolar form, each data bit being represented by means of four bits (1,1,0,0) for a binary "1" and (1,0,1,0) for a binary "0", a polarity alternation being effected every bit with a violation of polarity at each octet, comprising the steps of: separating the interface signal into its positive and negative components; producing a rectified signal from the said components; deriving from the rectified signal a bit timing signal; deriving the decoded data signal from the rectified signal and the timing signal; deriving from said components a signal representing the alternations of polarity; deriving from this latter signal and from the bit timing signal an octet timing signal; and comparing in phase the bit timing signal and the polarity alternation signal, a pulse for rephasing the bit timing signal being produced when the states of these two signals do not coincide at the time of a polarity alternation.

Abstract: A digital time division multiplex (TDM) telecommunication network is described wherein subscriber terminals are connected to a closed TDM loop which forms branch loops appropriately routed to remote subscriber groups or network sections. The branch loops may be bypassed by a connecting device in the event of a fault.

Abstract: A time division multiplex (TDM) switching network for a telecommunications system or the like is described. The network contains switching network units for causing time slots formed on connected TDM lines to be assigned on a space/time division basis. The TDM lines are formed into trunk groups, and the trunk groups, respectively, form the row and column lines of a matrix. The switching network units are arranged at the crosspoints of the trunk groups to form the crosspoint switching elements between the intersecting trunk groups or between lines of the same trunk group. Each switching network unit is constructed to have a capacity for completing a number of connections less than the number of connections the crosspoint with which it is associated is capable of carrying.

Abstract: Optical sensors may be arranged to give transmission or reflection of signals along optical fibers depending on the quantity to be measured. The outputs of several sensors may be simply multiplexed onto a single fiber (or pair) by putting a different delay line in series with each sensor. Similarly optical filters can be used separately or combined with the delay lines and/or space division multiplexing can be used to increase the number of sensors. Local frequency modulation of the sensors offer an additional means of multiplexing.

Abstract: A digital switch for switching word formatted PCM digital data is disclosed. The data of each PCM word is serially bit switched rather than being switched in parallel as in conventional PCM switches. This is achieved by time multiplexing corresponding word bits of respective incoming channels or inlets onto a single data highway to form a bit interleaved digital bit stream. Data on the highway is switched through a RAM under control of a control memory according to the required connections so as to rearrange the order of the data bits. The rearranged data is demultiplexed to the respective outgoing channels or outlets. To avoid less of alignment of word boundaries at the outlets, as between respective channels, the switch determines those connections which incur a switch cycle delay relative to those which do not.