Abstract: An encoding scheme for simplifying frame acquisition and access to an auxiliary channel information bit stream and apparatus for implementing same. A pair of incoming data channels are multiplexed onto three communicating data channels wherein one of the channels contains overhead bits and high speed data bits, a second channel contains auxiliary channel bits and high speed data bits and a third channel contains only high speed data bits. With this format, the operational frequency of the frame acquisition circuit is reduced compared to multiplexing to a single channel and the channel containing only high speed data can be used directly for bit error rate (BER) measurements.

Abstract: A digital circuit for the level measurement of PCM signals representing an analogue signal and encoded in accordance with a predetermined companding law comprising a selector circuit having position 0-n for selecting integers between 0 - n; a sampling circuit for successively sampling the input PCM signal 2.sup.n times, n being determined by the selector circuit; a connector circuit for converting each of the samples to its normalized power representation and for computing the average power of the samples; and means for determining the signal level equivalent of said average power in a conventional representation of power levels.

Abstract: A time division demultiplexer for demultiplexing synchronous digital signals which are interleaved wordwise comprising a shift register of length (m + 1) .multidot. n, where n is the number of bits/word and m is the number of interleaved signals, having a control unit and a first and second store having a total capacity of m .multidot. n bits and each having m parallel inputs and m outputs; said shift register having an output tap every n bits, said first store having m .multidot. q storage elements and said second store having m .multidot. r storage elements, where q and r are integers and q + r = n; said first store being loaded by the first q bits of m words appearing at said shift register input point and on the succeeding m - 1 of said taps counting from said input point of said shift register; said second store being loaded with the second r bits of said m words appearing at said output point and the preceding m - 1 of said taps of said shift register; said second store being loaded approximately (m .

Abstract: An asynchronous PCM common decoding apparatus decodes asynchronous PCM signals sent from a plurality of transmitter sources. The apparatus includes a plurality of receiver units each of which generate a digital signal to be decoded, a channel-number-designating signal, and a decode-requesting signal. One or more decoders are provided to decode the digital signals from the receiver units to analog signals. The decoders produce status signals indicating availabilities of the decoders for decoding the digital signals. A common control unit is responsive to both the decode-requesting signals and the status signals to successively allot a combination of a given receiver and a given decoder.

Abstract: An asynchronous, addressable multiplex system comprises a master station in parallel communication with a number of slave stations. Both the master and slave stations employ independently clocked UAR/T's (universal asynchronous receiver/transmitter) circuits for simultaneous data receiving and transmitting, the UAR/T's communicating directly with one another. The master station includes means for formatting data to be transmitted by its UAR/T into message blocks each several bytes long and intended for a particular slave station whose address is encoded only in the first byte of the block. The message blocks are transmitted separated from one another by gaps which are two bytes long. Each slave station receives all master station message blocks and has means for recognizing the gaps and for then comparing the address in the first byte thereafter with an assigned slave station address. If the addresses correspond, the entire message block is accepted by the slave station.

Abstract: At a channel bank, such as a D-type channel bank used in the Bell System, a steady visual alarm is exhibited if the source of a detected failure is at a location either within the channel bank or in the digital hierarchy of a digital transmission network. Unfortunately, a craftsperson is unable to distinguish between the two failure locations. To distinguish between the locations, apparatus for indicating the failure location to be in the hierarchy is situated between the hierarchy and the channel bank and, responsive to an alarm failure signal from the hierarchy, extends a predetermined cyclic code signal to the channel bank. Without modification of the channel bank and responsive to the code signal, a cyclic visual alarm in lieu of the prior art steady alarm is provided thereat.

Abstract: In a digital speech interpolation system, speech inactivity time is utilized to reduce the bit rate on a link between transmitter and receiver by compressing digital characters from a plurality of trunks onto a lesser plurality of channels. If the number of trunks having active speech samples exceeds the number of channels, an overload may exist. To mitigate overload, it is common to truncate one or more bits from a transmitted character. However, bit truncation leads to signal degradation. Of course, it is desirable to abate the degradation consistent with mitigating the overload. Unfortunately, the number of bits truncated from a character on a first trunk is typically more or less than the number of bits truncated from a character on a second trunk. As a result, the signal degradation may not be uniform. To obtain a more uniform signal degradation, the instant priority rotation arrangement rotates the starting point for assigning bits to a digital frame responsive to the activity status of the trunks.

Abstract: This disclosure relates to a demultiplexer for a pair of digital groups (digroups) which are synchronously multiplexed into a composite signal by bit interleaving the pair. The composite multiplex signal is coupled to each of a pair of gating circuits. A clock recovery circuit recovers the timing of the composite signal and generates therefrom a pair of phase inverted clock signals. These clock signals are respectively coupled to the two gating circuits to alternately enable the same and thereby steer the interleaved digroup bits to separate digroup receive units. A comparison circuit is coupled to each receive unit to compare the relative timing of the bits delivered thereto; this comparison utilizes the fact that multiplexing is done with the bits of one digroup preceding the bits of the other.

Abstract: A data communication system is described in which individual pulses or groups of pulses relating to specific items of information are multiplexed together to produce a pulse stream and this pulse stream is continually repeated so as to reduce the significance of errors in transmission which would be corrected automatically in the next transmission of the pulses relating to the incorrectly transmitted data. The system is described with reference to a data processing system for recording details and charges relating to manually connected telephone calls. Two-way communication between data entry and utilization means and a station control unit is provided in which the data rate for communication from the control unit to the data entry and utilization means is four times higher than that for communication from the data entry and utilization means to the control unit.

Abstract: A statistical multiplexing system is provided for computer communications, in which asynchronous user messages are transmitted from the individual terminals to the central processor, or other remote location, in random order. The messages are statistically multiplexed, with time slots being assigned in the communication channel as each message is received from the terminals, and with no time slots being assigned for idle periods, which greatly increases channel utilization. A buffer memory is required in the system to temporarily store messages from the terminals at statistical peaks. To improve channel efficiency, several characters for the same terminal may be collected together in the system to form an addressed data sub-block so as to reduce address label requirements. These sub-blocks are assembled into multiplexed data blocks by a microprocessor and stored in the buffer memory.

Abstract: The invention relates to switching matrices used in exchanges of time-division kind and to networks using that kind of matrices. It consists in utilizing at the input and output of a symmetrical time matrix, a multiplexer and a demultiplexer which enable the overall circuit to address an arbitrary IT (time slot) of an arbitrary incoming junction, to an arbitrary IT on an arbitrary outgoing junction. A network using only that kind of matrices is disclosed.

Abstract: A pulse code modulation (PCM) time division multiplex (TDM) automatic telephone exchange, comprising a series-to-parallel converter having incoming multiplex channel inputs and outputs, corresponding to the number of bits in a bit-group, a routing network having M inputs, each connected to an output of the series-to-parallel converter and a like number of outputs, and having a storage device therein, for simultaneously time and space switching information received in an incoming time slot to an outgoing time slot, and a parallel-to-series converter receiving a bit-group of one of the outgoing time slots on said M routing outputs. The operation of the telephone exchange is controlled by a time based device which synchronizes bit-group transfer in the routing network, the series-to-parallel converter, and the parallel-to-series converter, and also produces a periodic resynchronizing pulse.

Abstract: A bit error performance monitor in which the input signal is equally shared by two substantially identical monitors whose outputs in turn are connected to an adder. The output of the adder passes through a divider-by-2 to a counter.

Abstract: A bit error rate performance monitor unit for use in digital transmission links in which the signal input is equally divided between two demodulators of which one is disturbed, the combined output of said modulators being fed to an adder, the output of said adder being connected to a counter for continuously counting the bit error rate of the link.

Abstract: A device for permanent installation in series with a time division multiplex digital data transmission line for accessing data signals carried by the line without interruption or degradation of the signals. The device, referred to as a line access module (LAM), operates in a throughput mode in which incoming signals pass through the device without modification and a bypass mode in which the incoming signals are bypassed to an external common electronics circuit and reinserted in the outgoing transmission line.

Abstract: A satellite communications system provides automatic channel assignment without employing a dedicated signalling channel. A major station detects carrier-free forward channels and transmits on each a forward signal. A minor station hunts all available forward channels to ascertain and then monitor a carrier-free forward channel, detects the major station's forward signal and transmits a response signal on the corresponding carrier-free return channel while temporarily inhibiting reception by the minor station of any other signal from any other major station. The major station monitors all carrier-free return channels and detects the response signal to establish a link.

Abstract: A processor controlled communication switching system or PABX uses time division multiplexing with pulse width modulation of audio signals. Switching to establish communication paths between peripheral devices serviced by the system is distributed among the peripheral devices and controlled by command signals issued to the peripheral devices by a processor implemented common control. All peripheral devices transmit to the common control on a communication send line and receive signals from the common control on a communication receive line. The particular illustrated system services up to fifty two-way peripheral device ports and is inherently nonblocking.

Abstract: A plural channel amplitude modulated telephone carrier system having a plurality of transmitters to provide for the transmission of a like plurality of frequency division multiplexed, amplitude modulated carrier signals in a common direction along a transmission line to a remote termination of the transmission line, and an automatic carrier level coordination control circuit having a first circuit means for developing a d.c. control signal that varies as a predetermined function of the transmission line length, and a second circuit means connected to the first circuit means for controlling the transmit power of each of the aforesaid carrier signals as a function of its own carrier frequency and as a function of the d.c. control signal. The telephone carrier system may be of the station carrier type and may have two or more plural channel amplitude modulated carrier sub-systems, each having its own transmission line.

Abstract: A statistical multiplexing system is provided which includes two microprocessors with independent local memories, the microprocessors being designated as the "send microprocessor" and the "receive microprocessor," respectively. Communication between the two microprocessors is provided by an interprocess communication facility which comprises a first-in-first-out memory, and such communication is initiated by interrupt signals to the respective microprocessors. The send microprocessor assembles characters from different terminals, echos characters back to the different terminals in accordance with a local echoing function, collects characters from the same terminal into data sub-blocks with block time-out interrupts, multiplexes the data sub-blocks, forms the data sub-blocks into data blocks and transmits the data blocks to remote stations according to data destination addresses in the data blocks.

Abstract: A telephone disabling device for preventing outgoing calls while permitting a two-way conversation includes a disabling member having a cover portion extending over the dialing device. The member is hooked under a forward part of the telephone and the rear end thereof extends between the laterally spaced uprights forming the hand set cradle. A key lock carried by the disabling member is extendible into a rearwardly opening cavity in the telephone to prevent removal of the member. A modified form of disabling device prevents both outgoing calls and two-way conversation.