Patents Examined by David L. Talbott
  • Patent number: 7211889
    Abstract: A semiconductor package includes a wiring board, a semiconductor chip flip-chip bonded to the wiring board, an adhesive coated on the wiring board, a stiffener ring attached to the wiring board, and a heat spreader attached to the stiffener ring and the semiconductor chip. The stiffener ring includes a window through which the semiconductor chip is exposed and multiple through holes. A thermal interface material (TIM) coated on the back surface of the semiconductor chip. The stiffener ring is attached to the heat spreader by portions of the adhesive squeezed onto the upper surface of the stiffener ring via the through holes, and the semiconductor chip is attached to the heat spreader by the TIM. A method for manufacturing a semiconductor package includes: flip-chip bonding a semiconductor chip to a wiring board; coating an adhesive on the wiring board; and attaching a stiffener ring to the wiring board. The stiffener ring includes a window through which the semiconductor chip is exposed and through holes.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: May 1, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Bo Shim
  • Patent number: 7019221
    Abstract: A printed wiring board including a first printed wiring board and at least one second printed wiring board composed of a different material from a material of which the first printed wiring board is composed. The second printed wiring board is fixed to at least a part of the first printed wiring board.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: March 28, 2006
    Assignee: NEC Corporation
    Inventor: Yuji Noda
  • Patent number: 6995983
    Abstract: The present invention is a component carrier comprising a plate of insulating material having a plurality of apertures for accepting the leads of a thru-hole differential and common mode filter. Another embodiment comprises a surface mount component carrier comprised of a disk of insulating material having a plurality of apertures. The same concept for the above described carrier is also incorporated into several alternate embodiments, either independently or embedded within electronic connectors, or configured for use with electric motors. The overall configuration and electrical characteristics of the concepts underlying the present inventions are also described as an electrical circuit conditioning assembly which encompasses the combination of differential and common mode filters and component carriers optimized for such filters.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: February 7, 2006
    Assignee: X2Y Attenuators, LLC
    Inventors: Anthony A. Anthony, William M. Anthony
  • Patent number: 6914196
    Abstract: A reel-deployed printed circuit board for chip-on-board (COB) packages and a method for manufacturing COB packages using the reel printed circuit board are disclosed. The novel circuit board comprises an elongated, flexible base board and a plurality of unit boards defined within it by a plurality of slits cut through it. Each unit board comprises a plurality of bonding pads on its top surface, a plurality of contacts on its bottom surface, and a plurality of via holes that electrically connect the contacts to the bonding pads. The circuit board further comprises connection bars that connect the unit boards to the flexible base board. The method for manufacturing COB packages using the reel-deployed printed circuit board comprises the steps of forming the reel printed circuit board, attaching a semiconductor chip to it, connecting the semiconductor chip to the bonding pads, encapsulating the semiconductor chip, and separating the COB packages from the reel printed circuit board.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung Dae Cho
  • Patent number: 6888243
    Abstract: To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Yasuo Yamaguchi
  • Patent number: 6884944
    Abstract: A multi-layer printed wiring board having via holes is characterized by having the outer copper wifing circuit lines on a layer of an alkaline refractory metal which is adjacent to a thermosetting resin layer. An alkaline refractory metal which is insoluble is alkaline etching solutions, is electrodeposited on the surface of copper foil, then a thermosetting resin is applied to the surface and semi-cured to obtain a coated copper foil. The coated copper foil is bonded to one or both faces of an inner layer board having wirings on one or both of its faces. Then, the copper foil on a surface of this laminate is removed by alkaline etching, while selectively leaving the alkaline refractor metal layer. A laser beam is used to form via holes in both the alkaline refractory metal layer and the thermosetting resin layer simultaneously.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: April 26, 2005
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Fujio Kuwako
  • Patent number: 6864430
    Abstract: In order to provide a flexible oxide superconducting cable which is reduced in AC loss, tape-shaped superconducting wires covered with a stabilizing metal are wound on a flexible former. The superconducting wires are preferably laid on the former at a bending strain of not more than 0.2%. In laying on the former, a number of tape-shaped superconducting wires are laid on a core member in a side-by-side manner, to form a first layer. A prescribed number of tape-shaped superconducting wires are laid on top of the first layer in a side-by-side manner, to form a second layer. The former may be made of a metal, plastic, reinforced plastic, polymer, or a composite and provides flexibility to the superconducting wires and the cable formed therewith.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: March 8, 2005
    Assignee: Southwire Company
    Inventors: Raburn L. Hughey, Uday K. Sinha, David S. Reece, Albert C. Muller
  • Patent number: 6838755
    Abstract: A leadframe for semiconductor devices, including a region which is adapted to support a semiconductor device and a plurality of leads which are arranged so as to be directed toward the region, for mutual connection, by connecting wires connecting the leads and the semiconductor device. The leads include leads having at least two different lengths for the connection of connecting wires having different diameters.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: January 4, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Tiziani, Carlo Cognetti, Andrea Cigada
  • Patent number: 6838760
    Abstract: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: January 4, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Chad A. Cobbley
  • Patent number: 6838297
    Abstract: The invention provides a nanostructure including an anodized film including nanoholes. The anodized film is formed on a substrate having a surface including at least one material selected from the group consisting of semiconductors, noble metals, Mn, Fe, Co, Ni, Cu and carbon. The nanoholes are cut completely through the anodized film from the surface of the anodized film to the surface of the substrate. The nanoholes have a first diameter at the surface of the anodized film and a second diameter at the surface of the substrate. The nanoholes are characterized in that either a constriction exists at a location between the surface of the anodized film and the surface of the substrate, or the second diameter is greater than the first diameter.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: January 4, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den
  • Patent number: 6828511
    Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: December 7, 2004
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6809411
    Abstract: In order to obtain a minimal leakage inductance in a semiconductor component, it is necessary to provide at least two adjacent switching elements whose load current connection elements which are adjacent on one housing side to have different polarities. A multiplicity of even-numbered switching elements are advantageously disposed next to one another on an alignment line. The leads between the load current connection elements and the load current connections of the switching elements that are disposed next to one another advantageously run approximately orthogonally with respect to the alignment line. The assigned load current connection elements then alternately have the first and the second supply potential and this minimizes the leakage inductance.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: October 26, 2004
    Assignee: EUPEC Europaeische Gesellschaft fuer Leitungshalbleiter mbH
    Inventor: Martin Hierholzer
  • Patent number: 6806558
    Abstract: A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the transmission lines are formed at predetermined locations, each interconnect electrically connecting together a group of the transmission lines to form a conductor. The efficiency of the coupling between the lines in the different conductor is increased by positioning the lines such that both edge and broadside-coupling is realized. For example, at least one of the transmission lines in one of the conductors is positioned either above or below a transmission line in the other conductor to achieve broadside-coupling and laterally adjacent to another transmission line in the other conductor to achieve edge-coupling.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: October 19, 2004
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Thomas R. Apel
  • Patent number: 6787710
    Abstract: In holes formed in a multi-layer wiring board for transmitting differential signals, a first hole is formed, an insulating portion is formed by filling the first hole with an insulating resin, a pair of second holes is formed for transmitting the differential signals to the formed insulating portion, and the pair of second holes is arranged symmetrically each other with respect to a center axis of the first hole for forming a coaxial structure.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: September 7, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiaki Uematsu, Shinji Manabe
  • Patent number: 6784526
    Abstract: According to the present invention, for a module in which a plurality of integrated circuit devices are mounted in parallel, the inductance generated by the unit length of a branched signal line on a motherboard is so set that it is smaller for a branched signal line a longer distance from its branching point to its distal end, and is so set that it is larger for a branched signal line having a shorter distance from its branching point to its distal end, so that the time required for transmission of a signal from the branching point to the distal end of each branched signal line is the same.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: August 31, 2004
    Assignee: Fujitsu Limited
    Inventor: Tsutomu Mezawa
  • Patent number: 6753556
    Abstract: A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing gas is provided. Semiconductor structures comprising the metal silicate formed over a SiO2 layer are also disclosed herein.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: June 22, 2004
    Assignee: International Business Machines Corporation
    Inventors: Eduard Albert Cartier, Matthew Warren Copel, Frances Mary Ross
  • Patent number: 6753483
    Abstract: The present invention provides a printed circuit board, which includes a dielectric substrate having via holes formed in the thickness direction, and a conductor including a conductive filler is filled in the via holes. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity. The present invention also provides a method of manufacturing such a printed circuit board.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Patent number: 6734535
    Abstract: A semiconductor device comprising: a semiconductor chip (10) on which a plurality of electrodes are formed; a first flexible substrate (20) which is larger than the surface of the semiconductor chip (10) on which the electrodes (12) are formed, having a wiring pattern (22) formed thereon, and having the semiconductor chip (10) mounted thereon; a plurality of external terminals (38) electrically connected to the electrodes (12) by the wiring pattern (22); and a second flexible substrate (30) adhered to the first flexible substrate (20) avoiding the semiconductor chip (10).
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: May 11, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6730858
    Abstract: A circuit board for mounting a part having a plurality of bumps by ultrasonic bonding. The circuit board includes a main body and a conductive layer provided on the main body. The conductive layer has a conductive pattern having at least one bonding area configured to correspond to the plurality of bumps of the part. The conductive layer has an isolated notch part located proximate the at least one bonding area.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: May 4, 2004
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto, Kenji Honda
  • Patent number: 6724082
    Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventors: James A. McCall, Hing Y. To, Michael W. Leddige