Abstract: An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.

Abstract: Transmission line structure is composed of a pair of signal conductors which are embedded in one wiring region of a dielectric layer and a thickness in height of the signal conductor is larger than a width, and is constituted so that a coupling impedance between the adjacent signal conductors is lower than a coupling impedance between the signal conductor and another conductor formed in another wiring region, and thus to provide a multi-layer wiring board having a transmission line structure of high wiring density and excellent transmission characteristic.

Abstract: A method for upgrading or remediating semiconductor devices utilizing a remediation, adaptation, modification or upgrade chip in a piggyback configuration with a primary bare chip to achieve an upgrade, modification or adaptation of the primary chip or remedy a design or fabrication problem with the primary chip.

Abstract: A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: An integrated circuit package is constructed by attaching lower dies to a substrate that has bond fingers deposited on its surface. One lower die and its associated bond fingers are located offset from the center of the substrate. The lower dies are electrically coupled to the substrate's bond fingers with lower bond wires. An upper die is stacked on at least one of the lower dies. The upper die is electrically coupled, with bond wires, to the lower die upon which it is mechanically coupled. Each of the lower dies may be coupled to the other lower die with bond wire bridges that span the lower bond wires. The upper die may be electrically coupled, with bond wire bridges, to any or all of the lower dies.

Abstract: A semiconductor wafer (1) has a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and further has process control modules (4) which are each arranged in an exposure field (2), namely each in place of at least one chip (5).

Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Abstract: An electronic component mounted member includes a circuit board, an electronic component connected to the circuit board and an electrically conductive adhesive interposed between the electronic component and the circuit board. In a joining interface of the electrically conductive adhesive and an electrode of the circuit board, an intermediate layer that is formed of a thermoplastic insulating adhesive with a softening temperature of 100° C. to 300° C. is interposed between the electrically conductive adhesive and the electrode. An electrically conductive filler contained in the electrically conductive adhesive is present partially in the intermediate layer, thus allowing an electrical conduction between the electrically conductive adhesive and the electrode of the circuit board.

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract: The stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding-pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame by utilizing a conductive adhesive material. A connecting hole is formed in the outer end of the inner lead for better electrical connection when soldered. The entire resultant structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Abstract: Proper grounding of a printed circuit board to a grounding conductor by solving the problems in soldering a grounding terminal to a printed circuit board by reflow soldering, relating to a mounting structure of a grounding terminal on a printed circuit board formed by soldering a grounding terminal to the printed circuit board. Two joint surfaces having different surface areas are formed within the joint part of the grounding terminal, and the grounding terminal is soldered to the conductive pattern on the printed circuit board corresponding to the joint surfaces by using the solder having an amount corresponding to the surface area of each joint surface. Also the bending area as the center of elastic deformation of the contact part of the grounding terminal is formed at a predetermined distance away from the relatively small joint surface of the joint part.

Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.

Abstract: A lead frame includes a die pad, a suspension lead and a plurality of leads. The group of leads include at least three kinds of leads, including first, second and third leads. While the first lead and the third lead are connected to each other upon production of the lead frame, a connecting portion therebetween has a smaller thickness than that of the frame body so that the first lead and the third lead can be separated from each other in a subsequent step.

Abstract: A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).

Abstract: A hermetically sealing package for an optical semiconductor equipped with a light transmitting window whose light transmitting surface is inclined at least six degrees from the vertical line of the package bottom plate and which is joined to a cylindrical component on the package side wall by the use of a solder brazing material, in which the window material is made of a light-transmitting ceramic (such as alumina or spinel) plate in a substantially regular hexagonal or disk form in which a metallized portion is formed around the periphery, leaving a circular light transmitting portion in the center of the plate; and an optical semiconductor module that makes use of the package. The hermetically sealing package and the optical semiconductor module are easy and inexpensive to manufacture, have high reliability, and do not deform the plane of polarization.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system includes a first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, and to on module terminations of the second module; and a second path of conductors extending from the circuit board to the second module connector, to the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module, and to on module terminations of the first module.

Abstract: A multilayer-wiring substrate having a via hole structure and method for fabricating the same. Referring to FIGS. 1(a) and 1(b), after a via-hole 5 is formed by exposure and development in lithography or by laser-drilling, a bottom portion of the via-hole 5 is subjected to resin-etching so as to expose a surface 4A of a lower conductor 4 as shown in FIG. 3(b). The exposed surface 4A of the lower conductor 4 is chemically etched so that the conductor 4 is undercut. As a result, undesired material 5B such as adhered residual resin shown in FIG. 3(b) is completely removed. In etching the conductor 4 at the bottom of the via hole 5, the lower conductor 4 is preferably etched in an amount of 5-30% of the thickness of the lower conductor 4 to form a depression or recess 6A at a via hole bottom 5C as shown in FIG. 3(b), thereby reliably establishing electrical continuity between the lower conductor 4 and the upper conductor 8 by means of a via-hole conductor 7 as shown in FIG. 3(c).

Abstract: A protection device for an electrical component that has a protective housing and a terminal cap. The protective housing has a base with a contact hole therethrough for accommodating an electrical terminal pin. A projecting perimeter wall extends from the base. A sleeve resides within the perimeter wall, and a terminal cap is captured between the sleeve and the protective housing. A method of assembling a battery and an electrical component with such a protection device is also disclosed.

Abstract: The present invention discloses an image sensing semiconductor package and manufacture method thereof utilizing the plastic leaded chip carrier (PLCC) manufacture process to produce image sensing chips with a cheaper plastic carrier, and it also seals dry high-pressure gas inside the image sensing chip in the manufacture process. Therefore, when the image sensing chip is used in a device, it can prevent moisture in the air from entering into the interior of the image sensing component due to pressure difference that will shorten the lifespan of the image sensing chip. The invention also provides a component rinsing procedure for the image sensing semiconductor package manufacture process, so that no environmental factor of the manufacture process such as humidity and dust particles will affect the sensitivity of the chip or the normal display of the screen, and hence lower the defective rate of the product.