Patents Examined by David L. Talbott
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Patent number: 6670215Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 30, 2002Date of Patent: December 30, 2003Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6670633Abstract: A microelectronic device is provided including an integrated circuit mounted to a substrate. A break through multiple conductive layers of the substrate corresponds to a break in the power planes of the integrated circuit. The breaks in the substrate and in the integrated circuit allow for a rotational burn-in of a first portion and a second portion of the integrated circuit.Type: GrantFiled: December 29, 2000Date of Patent: December 30, 2003Assignee: Intel CorporationInventor: Mike Mayberry
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Patent number: 6670558Abstract: Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.Type: GrantFiled: August 22, 2001Date of Patent: December 30, 2003Assignee: Intel CorporationInventors: Sanjay Dabral, Ming Zeng, Dillip Sampath, Zale T. Schoenborn
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Patent number: 6670707Abstract: An integrated circuit chip including a circuit board unit and a plurality of contact pads on a top surface of the unit. A die having a plurality of solder pads is positioned adjacent the circuit board unit with the solder pads wire-bonded to the contact pads. A lead frame having connecting leads is positioned on the circuit board unit with the leads connected to the solder pads via a conductive contact layer. A plastic layer encapsulates the circuit board unit and at least a portion with the lead frame.Type: GrantFiled: February 22, 2001Date of Patent: December 30, 2003Inventor: Ming-Tung Shen
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Patent number: 6670559Abstract: An electromagnetic shield device for printed circuit boards (PCBs) which, in one embodiment, is made of conductive material and comprised of two parts. In another embodiment, the device is a singular element. In both examples, press-fit or compliant pins may be used to electrically couple the device to the PCB's ground layer. Alternatively, projecting pins or flat conductive plates can be used to provide this coupling. The device is also adjustable to accommodate PCBs of varying thicknesses. The device provides for added PCB stiffness while assuring prevention of electromagnetic radiation from the PCB's edge.Type: GrantFiled: December 10, 2001Date of Patent: December 30, 2003Assignee: International Business Machines Corp.Inventors: Bruno Centola, Claude Gomez, Patrick Michel, Jacques Feraud
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Patent number: 6664485Abstract: The present invention provides a printed circuit board and a method for the production of a printed circuit board having fine-line circuitry and greater aspect ratio on a subcomposite with plated through holes. A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.Type: GrantFiled: February 7, 2001Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Anilkumar C. Bhatt, Voya R. Markovich, Irving Memis, William E. Wilson
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Patent number: 6664479Abstract: A flexible printed circuit board (FPC) comprises a base film; a base film side adhesive layer provided on the base film; a metal foil layer on which a pattern circuit is formed, provided on the base film side adhesive layer; and a cover layer side adhesive layer provided on the metal foil layer, wherein at least one of the base film side adhesive and the cover layer side adhesive layer has a higher glass transition temperature than an operating temperature of the flexible printed circuit board, so that the FPC has a stable flexibility at high temperature.Type: GrantFiled: April 27, 2001Date of Patent: December 16, 2003Assignee: Fujikura Ltd.Inventors: Nobuo Tanabe, Kenichi Okada, Yukihiko Kurosawa, Takayuki Imai, Sadamitsu Jumonji, Masahiko Arai, Masahiro Kaizu
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Patent number: 6664643Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.Type: GrantFiled: May 10, 2001Date of Patent: December 16, 2003Assignee: Seiko Epson CorporationInventor: Yoshiaki Emoto
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Patent number: 6664616Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is smaller in thickness than the tape base material 1a, and then sealing is performed using a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a is set to correspond to a stress neutral plane of the TCP as a whole.Type: GrantFiled: July 20, 1999Date of Patent: December 16, 2003Assignee: Hitachi, Ltd.Inventors: Kunihiro Tsubosaki, Toshio Miyamoto
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Patent number: 6665196Abstract: A shielding cover for a terminal device of an electric appliance and a compressor assembly includes first and second receiving parts which can receive selectively two or more terminal devices (overload protectors) formed in different shapes are integrally formed at the shielding cover. Accordingly, since the shielding cover can be used in common regardless of the shapes of the terminal devices, the whole manufacturing cost of an electric appliance such as a compressor assembly can be reduced.Type: GrantFiled: February 8, 2001Date of Patent: December 16, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Kwang-Woo Jang
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Patent number: 6664480Abstract: A circuit board substrate assembly includes a generally planar circuit board substrate material having a longitudinal axis extending along a length of the substrate material between a first end and a second end thereof. The circuit board substrate material further has a first edge and a second edge extending along the length of the circuit board substrate material between the first end and the second end. A plurality of openings are defined in the substrate material. Each opening extends between a first distance from the first edge of the circuit board substrate and a second distance from the second edge of the circuit board substrate. Further, each opening separates adjacent circuit forming regions lying along the longitudinal axis and has first and second opposing end portions.Type: GrantFiled: May 25, 2001Date of Patent: December 16, 2003Assignee: Micron Technology, Inc.Inventors: Zane Drussel, Derek Hinkle
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Patent number: 6664622Abstract: A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material and joined together to form a frame around an area substantially the same as the area of the components board. A plurality of metal pins are located in the frame, each having one end extending from said frame such that these ends can be soldered to the components board concurrently with the solder attachment of the components to the board. The other ends of the pins can be formed so that they are adjusted for either through-hole attachment to circuit boards, or for surface mounting.Type: GrantFiled: February 9, 2001Date of Patent: December 16, 2003Assignee: Texas Instruments IncorporatedInventors: Kristopher K. Neild, Claude Fernandez, Charles Schaefer
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Patent number: 6664484Abstract: A connection component for making connections to a microelectronic element is made by providing leads on a surface of a polymeric layer and etching the polymeric layer to partially detach the leads from the polymeric layer, leaving a portion of each lead releasably connected to the polymeric layer by a small polymeric connecting element which can be broken or peeled away from the lead. Leads in a connecting element may be covered by an insulating jacket applied by a coating process, and the insulating jacket may in turn be covered by a conductive layer so that each lead becomes a miniature coaxial cable. This arrangement provides immunity to interference and facilitates operation at high speeds.Type: GrantFiled: January 28, 2002Date of Patent: December 16, 2003Assignee: Tessera, Inc.Inventors: Belgacem Haba, Konstantine Karavakis
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Patent number: 6664482Abstract: A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.Type: GrantFiled: May 1, 2000Date of Patent: December 16, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ian P. Shaeffer, Everett Basham, Christopher D. Price
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Patent number: 6661081Abstract: Attaining improvement of the reliability and standardization of the lead frame. A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a≦2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.Type: GrantFiled: October 18, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Patent number: 6660942Abstract: A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elasticity underlayer made of a material having a lower modulus of elasticity than that of a base material of the wiring substrate is disposed between the base material of the wiring substrate and each of the electronic-part mounting pad and the rerouted wiring. A method of manufacturing the wiring substrate and a semiconductor device using the wiring substrate are also disclosed.Type: GrantFiled: April 5, 2001Date of Patent: December 9, 2003Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Takashi Kurihara
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Patent number: 6660946Abstract: A pin standing resin substrate comprises: a resin substrate having a substantially plate-shaped main surface and comprising one of a resin and a composite material containing a resin, with a pin-pad exposed from the main surface; and a pin solder-jointed to the pin-pad, wherein the pin has been subjected to thermal treatment so as to soften the pin, and comprises a rod-like portion and an enlarged diameter portion having the same material as the rod-like portion, the enlarged diameter portion having a larger diameter than the rod-like portion and being formed at one end of the rod-like portion, and at least the enlarged diameter portion is soldered to the pin-pad.Type: GrantFiled: April 10, 2001Date of Patent: December 9, 2003Assignee: NGK Spark Plug Co., Ltd.Inventors: Hajime Saiki, Noritaka Miyamoto
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Patent number: 6660944Abstract: A circuit board having a plurality of solder bumps is provided. The solder bumps are flattened and leveled at the tops so that the coplanarity of the solder bumps is 0.5 &mgr;m or less per 1 mm. The flattened and leveled tops of the solder bumps are formed by cold pressing, hot pressing or grinding. Method of forming such solder bumps and jigs used for carrying out such methods are also provided.Type: GrantFiled: March 28, 1997Date of Patent: December 9, 2003Assignee: NGK Spark Plug Co., Ltd.Inventors: Haruhiko Murata, Yukihiro Kimura, Masashi Inaishi
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Patent number: 6660945Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.Type: GrantFiled: October 16, 2001Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Donald S. Farquhar, Konstantinos I. Papathomas
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Patent number: 6657130Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.Type: GrantFiled: September 20, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Peter D. Van Dyke, Daniel P. O'Connor