Abstract: An adhesive system and a method of adhesion for a ball grid array semi-conductor device package facilitate the encapsulation of a die attached to a circuit board. A material is added between a die and a circuit board tape, and is oriented perpendicular to a conventional two-piece tape system used to attach the die to the circuit board. The material, which is located across from a gate through which an encapsulation compound is injected to form a package, acts as a diversion dam. The material thereby enables the injected encapsulation compound to fill a wirebond slot last and avoid an overflow which might otherwise damage the ball grid array.

Abstract: Terminating resistances are provided to at least some pins of an ASIC or other multi-pin component mounted on a surface of a circuit board, by positioning a second circuit board on the surface of the main circuit board substantially opposite, and preferably aligned with or overlapping, the multi-pin component. The second circuit board accommodates a resistor such as a printed resistor, surface mount resistor or buried resistor. Preferably, vias in the main circuit board connect pins of the ASIC to terminating resistors. Preferably one or both of the ASIC and the second circuit board are coupled to the main circuit board by a ball grid array.

Abstract: In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.

Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.

Abstract: A multilayer circuit board formed by integrally laminating a plurality of printed wiring boards in a multilayer structure so as to provide air gaps therebetween. An insulating layer is formed on each of both surfaces of a metal core substrate having through-hole forming apertures and a printed wiring layer is formed on the each insulating layer. Metal projections integrally formed on the metal core substrate serve as bonding electrodes between the adjacent wiring boards in the multilayer structure. The width of the air gap provided between the adjacent wiring boards is determined by the height of the metal projections.

Abstract: A noise protection sheet 1 is stuck on an IC chip C loaded on a circuit board 31 to control the noise generated from the IC chip C. The noise protection sheet 1 includes a metallic sheet 2 and insulating films 3 sandwiching the metallic sheet from both front and rear surfaces thereof. The metallic sheet 2 has, at its one end, an extending portion 7 to be connected to a land 32 serving as a grounding terminal on the circuit board 31. In this configuration, the noise protection sheet can effectively solve a noise problem in an electronic component.

Abstract: In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.

Abstract: A circuit substrate utilizes buried edge connectors. The buried edge connectors are mechanically disposed within the edge of the substrate and have substantial thickness. The configuration and method for making the same provides relatively large edge connectors mechanically constrained in the edge of a circuit substrate.

Abstract: An RF amplifier module includes PC boards laminated atop a bottom conductor plate. The boards include an RF semi-conductor amplifier chip mounted in a well extending to the bottom plate disposed in electrical connection with the chip.

Abstract: A transistor (200) is provided with a semiconductor chip (1) inside a resin package (20). An outer lead (41, 42, 43, 44) is arranged on a first side surface (23) of the resin package (20) to serve as an external drain electrode. A lead frame (5) includes the outer lead (41, 42, 43, 44) and a sheet-like portion (51). The sheet-like portion (51) is connected to a first surface (1a) of the semiconductor chip (1) for holding a drain electrode. An outer lead (45, 46, 47, 48) is arranged on a second side surface (24) of the resin package (20) to serve as an external source electrode. The outer lead (45, 46, 47, 48) is connected by a wire (4) to a second surface (1b) of the semiconductor chip (1) for holding a source electrode. An ejector pin site (22) formed on a top surface (21) of the resin package (20) is located on the side of the first side surface (23).

Abstract: A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, preferably epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

Abstract: A small multichip module has a mother chip and a stack chip. The stack chip is stacked on the mother chip. The mother chip includes a first bonding pad located in a circuit area. A bonding pad of the stack chip is wire-bonded with the bonding pad of the mother chip.

Abstract: Each wiring layer of a multilayered wiring substrate includes signal wirings disposed in parallel with one another, and dummy wirings disposed at each side parallel to the signal wirings of the signal wiring group made by signal wiring, respectively. The dummy wirings have the same shape as the signal wirings, and are disposed in parallel to the signal wirings at the same intervals as that in the signal wirings. Through holes are formed in the respective clearances among the signal wirings. Dummy through holes having the same shape as the through holes are formed between the dummy wiring and signal wiring. A conductive layer is formed on the inner wall of the through holes. The multilayered wiring substrate is able to reduce or eliminate the delay time difference between signals that propagate along the signal wirings.

Abstract: Signal wirings 22, 23 are formed on a pair of substrates 20, 21, and the substrates are joined together through an insulating layer 24 so that the signal wirings 22, 23 are placed in parallel and facing to each other. The surfaces of the overlapping faces of the signal wirings 22, 23 are made smooth, and the roughness of the same surfaces is smaller than the skin depth &dgr;s due to the skin effect, preferably less than one third, for minimizing the increase in the electric resistance due to the skin effect.

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.

Abstract: A semiconductor package and a fabricating method thereof are proposed. The semiconductor package includes a semiconductor chip; a plurality of leads surrounding the chip and formed with a plurality of connecting mechanisms and strengthening structures; and an encapsulant for encapsulating the chip and the leads. The foregoing semiconductor package eliminates the use of a die pad, allowing the thickness of the package to be reduced and a surface of the chip to be exposed to the outside of the encapsulant for improving the heat dissipating efficiency thereof. The leads have the same height as the semiconductor package, allowing upper and lower surfaces of the leads to be exposed to the outside of the encapsulant, which further enhance the dissipation of heat generated by the chip in operation.

Abstract: An electronic component includes a substrate (210, 1510), a device (221, 222) supported by the substrate and including a first bond pad (223, 224, 225, 226), and a cap (231, 232, 631, 731, 732, 1531, 1532) overlying the substrate. The cap includes a second bond pad (241, 242, 243, 244) at an outside surface of the cap, a third bond pad (245, 246, 247, 248) at an inside surface of the cap and electrically coupled to the first bond pad, and an electrically conductive via (251, 252, 254, 751, 752, 753, 754) extending through the cap and electrically coupling together the second and third bond pads.

Abstract: A circuit board having a dielectric substrate, a grounding surface formed on at least one surface of the dielectric substrate, and transmission lines formed on one surface of the dielectric substrate for transmitting electrical signals. At least a portion of each of the transmission lines is isolated from an upper surface of the dielectric substrate to reduce the effective permittivity between the transmission lines and the grounding surface and a dielectric loss therebetween. In a method of manufacturing a circuit board, first, a sacrificial layer is formed on a dielectric substrate. Next, supporter patterns and transmission line patterns are formed by patterning the sacrificial layer. Then, supporters and transmission lines are formed in the supporter patterns and transmission line patterns, respectively. Following this, the sacrificial layer is removed so that the transmission lines are isolated from the upper surface of the dielectric substrate.

Abstract: A multilayered switching structure is disclosed for the development and the production of an apparatus based on microelectronic components and semiconductor devices. The structure may widely be used in the production of multilayered printed circuit cards and switching structures for monocrystalline modules. The multilayered switching structure includes a plurality of layers of a dielectric material which include electroconductive tracks on their surfaces and which consist of switching layers. This structure also includes contact nodes consisting of metallized contacts which are aligned with each other and which are electrically and mechanically connected together by an electroconductive binding material. The contact nodes are made in the form of splices arranged between the contacts. In a second embodiment, the multilayered switching plate includes electroconductive tracks provided on both sides of each switching layer and are connected together within the limits of each layer by metallized junction openings.