Abstract: The present invention relates to a method and system to suppress or eliminate light shift in an optical pumping system, such as an atomic clock. The method uses modulation of a radiation source, such as a radio frequency or microwave source, to simultaneously lock the frequency of the radiation source to an atomic resonance and lock the frequency of the optical pumping source in order to suppress or eliminate light shift. In one embodiment, the method of the present invention directly utilizes the out-of-phase channel of a lock-in amplifier to additionally lock an optical pumping source to a zero-light-shift frequency, where the in-phase channel is used to lock the frequency of the radiation source to an atomic resonance.

Abstract: In a signal communication device, a frequency-selective filter has at least one component that is biased by a control signal to establish a center frequency of the frequency-selective filter. A closed-loop bias generator is provided to generate the control signal and to adjust the control signal based, at least in part, on a comparison of the control signal and a reference signal.

Abstract: An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal generation circuit changes a capacitance of the capacitors that are affecting the output clock signal in response to a change in the control signals. The apparatus also includes measurement circuitry that determines a calibration number of the fine capacitors having a combined capacitance that most closely matches a capacitance of one of the coarse capacitors.

Abstract: Various example embodiments are disclosed herein. According to an example embodiment, a method may include receiving a plurality of data symbols, generating a continuous phase modulated waveform based on the data symbols, generating a plurality of coefficients which represent the continuous phase modulated waveform, and wirelessly transmitting the plurality of coefficients via a plurality of subcarriers.

Abstract: There is described a method and an apparatus for pulse width modulation with a predefined switching period having an adjustable ratio of the switch-on duration to the switch-off duration, in which a quantized signal is converted into a pulse-width-modulated signal and is generated in the form of a discrete pulse sequence of switch-on operations and switch-off operations with the predefined switching period, the switching edge for the switch-on duration and/or the switch-off duration being determined on the basis of the ratio of the switch-on duration to the switch-off duration.

Abstract: In an exemplary embodiment, a free running VCO has two modes: a normal operating mode and a calibration mode. In the calibration mode, the free running VCO is phase lock looped with itself instead of a calibration VCO. Furthermore, in an exemplary embodiment, a tuning voltage for the free running VCO is adjusted to offset any tuning error. In addition, in various embodiments a reference crystal oscillator used in the phase lock loop is located on a DSP module instead of on the RF module. In yet another exemplary embodiment, the free running VCO is the only high frequency VCO on a radio frequency module.

Abstract: Dead time compensated complementary pulse width modulation (PWM) signals are derived from a PWM generator by first applying time period compensation to the PWM generator signal based upon the direction of current flow in an inductive load being controlled by the PWM generator. Dead time is then applied to the compensated PWM generator signal for producing complementary dead time compensated PWM signals for controlling power switching circuits driving the inductive load.

Abstract: A method of fabricating a hermetic terminal includes: joining and firing wherein a bar-shaped member to be a lead is inserted into a ring, and they are fired to form a hermetic terminal intermediate having the bar-shaped member fixed in the ring; flattening wherein an end part of the bar-shaped member to be the inner lead portion of the lead is flattened to form a stair portion; and shaping wherein an end part of the stair portion is cut to shape the stair portion into a predetermined shape, wherein in the joining and firing step, a solid round bar longer than the lead is used as the bar-shaped member, and one end side of the bar-shaped member to be the inner lead portion is inserted into the ring so that the one end side is longer than the inner lead portion in the hermetic terminal as a completed product.

Abstract: A pulse modulation method divides code comprising 4N-bit data into 2-bit units of data. For each pulse signal having a fixed pulse width tw, a code modulated signal is generated by pausing between pulse pause intervals Tr. An adjusted time width of between ½ and 1 times the fixed pulse width tw is taken to be ?t. One of time widths 0, ?t, 2?t, and 3?t is added to a fixed pause period tm of time intervals according to a corresponding value of the 2-bit data. If the sum total time TD of the code modulated signal is an interval of at least [(2tw+2tm+3?t)N+?t], each pulse pause interval Tr is substituted by a pulse pause interval Tr corresponding to the inverted 2-bit data. An inversion flag signal expresses that inversion information is added to the code modulated signal.

Abstract: A surface-mount type crystal oscillator includes a container body with a recess, a first holding terminal and a second holding terminal provided in the recess, a crystal blank secured to the first and second holding terminals, and an IC chip including a first terminal and a second terminal on respective opposite sides of one end of the IC chip, the first and second terminals being used to electrically connect the amplification element within the IC chip to the crystal blank. In the recess, the first connection terminal is connected, by wire bonding, to one of a first circuit terminal connected to the first holding terminal and a second circuit terminal connected to the second holding terminal. The second connection terminal is connected, by wire bonding, to one of a third circuit terminal connected to the first holding terminal and a fourth circuit terminal connected to the second holding terminal.

Abstract: A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation.

Abstract: AM (Amplitude Modulation) demodulation system (36) for an RFID reader device (31), of the type comprising a demodulator (6) for receiving from a RFID tag (11) an AM (Amplitude Modulation) wave (20) having a predetermined frequency (f) and for retrieving, from the AM wave (20), a demodulated output (6a) associated to predetermined positive or negative Amplitudes of said AM wave (20). The AM demodulation system comprises at least a second demodulator (26) for receiving the AM wave (20) and retrieving a second demodulated output (26a) associated to Amplitudes opposite to the predetermined positive or negative Amplitudes and a block (27) having, in input, the demodulated output (6a) and the second demodulated output (26a) and returning, in output, an enforced demodulated output (30) with a frequency (f1) greater than the predetermined frequency (f).

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.

Abstract: A clock frequency modulator for an oscillator having a digital circuit for the generation of a signal modulating the clock frequency, the digital circuit adapted to obtain, from the signal generated by the oscillator, a first pulse signal having a lower frequency than the clock frequency of the oscillator, a digital counter adapted to count the pulses of the first signal and to produce a digital signal and a digital-to-analog converter adapted to convert the digital signal in the signal for modulating the clock frequency of the oscillator.

Abstract: A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

Abstract: A method and apparatus for automatic frequency correction in a demodulation circuit. The apparatus includes a demodulator, a frequency offset estimator, a frequency controller, and an oscillator. The oscillator provides a receiver clock signal which the demodulator employs to demodulate a modulated signal. The frequency offset estimator estimates an offset between a carrier wave frequency of the modulated signal and a frequency of the receiver clock signal. The frequency controller provides a frequency control signal to the oscillator for adjusting the frequency of the receiver clock. While the estimated offset is outside of an adjustment range, the frequency controller maintains the frequency control signal at its previous value. The frequency controller also adjusts the adjustment range based on past error signal values.

Abstract: Systems and methods for minimizing startup transients in digital audio controllers that may result in audible artifacts in the output of an audio amplification system. One embodiment comprises a digital PWM amplifier that includes a mechanism for controlling the amount of dead time in the audio output signal. When the amplifier starts up, the PWM signals provided to the output stage are simultaneously deasserted (i.e., there is dead time) for most of each switch period. The amount of dead time is gradually reduced over a series of switch periods until a nominal operating amount of dead time in each switch period is reached. Thus, the PWM signals are slowly ramped up from having a very large percentage of dead time (e.g., nearly 100%) to having a very small percentage of dead time (e.g., 1-2% to prevent shoot-through.

Abstract: A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.

Abstract: In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted.

Abstract: A digital phase locked loop has a digital controlled oscillator, a feedback loop coupled to the output of said digital controlled oscillator, a phase detector for comparing a feedback signal from said feedback loop with a reference signal to produce a phase error signal, and a low pass filter for filtering the phase error signal for controlling said digital controlled oscillator. A bandwidth calculation unit calculates the required filter bandwidth based on the phase error. The bandwidth calculation unit then controls the bandwidth of said low pass filter, which is thus adaptively adjusted in accordance with the phase error.