Patents Examined by David Mis
  • Phase recovery circuit
    Patent number: 7728683
    Abstract: A phase recovery circuit for avoiding noise interfering with the clock signal generated from an oscillator is disclosed. The phase recovery circuit includes a noise detector, a phase detector, and a phase locker. The noise detector detects noise and accordingly generates a noise detecting signal. The phase detector is triggered by the noise detecting signal for detecting the phase of the clock signal and accordingly generating a phase detecting signal. The phase locker locks the phase of the clock signal to a predetermined phase within a predetermined period after the occurrence of the noise detecting signal, and after the predetermined period, the phase locker releases the clock signal. In this way, the phase of the clock signal is not affected by noise.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: June 1, 2010
    Assignee: Leadtrend Technology Corp.
    Inventor: Ju-Lin Chia
  • Direct digital synthesizer for reference frequency generation
    Patent number: 7724097
    Abstract: A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 25, 2010
    Assignee: Resonance Semiconductor Corporation
    Inventors: L. Richard Carley, Anthony L. Tsangaropoulos, Esa Tarvainen
  • System and method of shaping a power spectrum in PWM amplifiers
    Patent number: 7724105
    Abstract: In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: May 25, 2010
    Assignee: Silicon Laboratories, Inc.
    Inventors: Jeffrey D. Alderson, John M. Khoury, Richard Gale Beale
  • Sigma delta digital to analog converter with wide output range and improved linearity
    Patent number: 7719369
    Abstract: A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively proportionate to the most significant bits (MSBs) and least significant bits (LSBs) of a received digital value. The two portions are added to generate an analog output representing the strength of the digital value. In an embodiment, the single DAC contains a set of current sources, with some of the current sources (determined by the value of the MSBs) being connected to provide the corresponding output currents on a first path. Some of the other current sources, determined by a value of the LSBs, are controlled to be connected to provide the corresponding output currents on a second path. The time durations the currents are connected to the second path, are determined by the output of a sigma delta modulator.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: May 18, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Anant Shankar Kamath, Biman Chattopadhyay
  • Device and method for generating a signal with predefined transcient at start-up
    Patent number: 7719373
    Abstract: A device and a method are presented for generating an intermitted oscillating signal comprising a plurality of oscillating portions separated from each other in time. The device and method are suited for communication systems, in particular for Ultra-Wide Bandwidth (UWB) applications. The device comprises a variable oscillator for generating the oscillating portions; switching circuitry for switching on/switching off the variable oscillator at the beginning/end of each oscillating portion; and circuitry for setting initial conditions in the variable oscillator to impose a predefined transient and a characterizing frequency upon each start-up.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: May 18, 2010
    Assignee: IMEC
    Inventors: Julien Ryckaert, Jan Craninckx
  • Configurable reset circuit for a phase-locked loop
    Patent number: 7719368
    Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: May 18, 2010
    Assignee: Agere Systems Inc.
    Inventors: Paul Jeffrey Smith, Travis A. Bradfield, Jeffrey K. Whitt
  • PLL circuit
    Patent number: 7719366
    Abstract: Disclosed herein is a phase lock loop (PLL) circuit capable of executing digital control of an oscillation circuit thereof by using a dividing ratio represented by a digital value obtained by dividing an oscillation frequency by a reference frequency. The PLL circuit includes a phase comparator for comparing the digital value obtained by converting the dividing ratio with a digital value representing each cumulative addition value of a clock count expressed in a decimal-point format representing the oscillation signal in each period of a reference signal, a loop-gain control section configured to control the loop gain of the PLL circuit, and an output converging section configured to converge an output by the phase comparator.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: May 18, 2010
    Assignee: Sony Corporation
    Inventor: Shinichiro Tsuda
  • Spread spectrum clock and reference signal generator
    Patent number: 7719371
    Abstract: Exemplary embodiments of the invention provide a system, method and apparatus for spread spectrum functionality for a free-running, reference harmonic oscillator. In an exemplary embodiment, an apparatus comprises a reference oscillator adapted to provide a reference signal having a reference frequency; and a spread spectrum controller adapted to control the reference oscillator to generate a spread-spectrum reference signal at a plurality of different reference frequencies during a predetermined or selected time period. An exemplary apparatus may also include a coefficient register adapted to store a plurality of coefficients and a plurality of controlled reactance modules responsive to a corresponding coefficient of the plurality of coefficients to modify an amount of reactance effectively coupled to the reference oscillator.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: May 18, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Scott Michael Pernia, Gordon Carichner, Eric Marsman, Michael Shannon McCorquodale
  • Monitoring and compensating for real time local circuit speed in an integrated circuit
    Patent number: 7714670
    Abstract: An integrated circuit comprises an oscillator that generates an oscillator signal. A first counter generates a first count based on transitions of the oscillator signal. A first circuit generates a match signal based on the first count and a reference count. A second counter generates a second count that is initialized at a starting count and adjusts the second count based on transitions of a reference clock signal. An output circuit outputs an oscillator speed based on the second count and the match signal. The oscillator speed is defined by a range that is independent of a frequency of the reference clock signal.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: May 11, 2010
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Reuven Ecker, David Moshe
  • Method for voltage limitation in a transponder
    Patent number: 7710213
    Abstract: A circuit for voltage limitation is provided in a transponder with a resonant circuit, which comprises at least one inductor, a capacitor, a depletion layer component with an input, output, and a control input, a first resonant circuit terminal, which is connected to the input of the depletion layer element, and a second resonant circuit terminal, which is connected to the output of the depletion layer element, whereby there is a connection between the control input of the depletion layer component and the first resonant circuit terminal and the second resonant circuit terminal. A method for voltage limitation in a transponder is provided, whereby for voltage limitation in the transmitting and receiving resonant circuit, the control terminal of the depletion layer element is driven by the voltage of the first and second resonant circuit terminal.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: May 4, 2010
    Assignee: Atmel Automotive GmbH
    Inventors: Martin Berhorst, Alexander Kurz, Peter Schneider
  • Pulse width modulation structure enabling regulated duty cycle
    Patent number: 7710214
    Abstract: A pulse width modulation (PWM) structure enabling regulated duty cycle includes a DC power supply unit, a signal generating unit, a voltage-dividing resistor unit, a reference voltage unit, and a comparing unit. When the DC power supply unit supplies a voltage signal to the voltage-dividing resistor unit, the latter receives the voltage signal and sets voltage levels before sending the voltage signal to the signal generating unit, so that a waveform signal generated by the signal generating unit regulates its voltage levels according to the received voltage signal before sending the waveform signal to the comparing unit. The comparing unit receives and compares the signals from the signal generating unit and the reference voltage unit, and outputs a comparison signal for driving a fan motor to operate, so that the finally output signal is substantially linear and smooth.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: May 4, 2010
    Assignee: Anpec Electronics Corporation
    Inventor: Ching-Sheng Li
  • Design structure for improved current controlled oscillation device and method having wide frequency range
    Patent number: 7710206
    Abstract: A design structure embodied in a machine readable medium used in a design process includes a current controlled, phase locked loop device having a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ram Kelkar, Anjali R Malladi
  • Synchronously stackable double-edge modulated pulse width modulation generators
    Patent number: 7705689
    Abstract: Synchronously stackable double-edge modulated pulse width modulation generators are disclosed. An example pulse width modulation generator includes a ramp generator to generate first and second ramp signals that interact to form a virtual ramp signal; and a comparator module coupled to the ramp generator configured to produce a pulse width modulated signal based on a comparison between the virtual ramp signal and an input signal.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: April 27, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: William Todd Harrison, Xuening Li, Stefan Wlodzimierz Wiktor
  • Radio frequency modulator
    Patent number: 7701308
    Abstract: A radio frequency modulator system having a radio frequency amplifier controlled by a pulse modulator. The pulse modulator includes: a first switching circuit response to an input pulse for coupling a dc voltage relative to a reference potential to the output electrode when the radio frequency signal is to be amplified by the radio frequency amplifier and for decoupling the dc voltage from the output electrode when the radio frequency signal is to be decoupled from the output electrode wherein charge is stored in the storage element when the dc voltage is coupled to the output electrode; and: a second switching circuit responsive to the input pulse for discharging the stored charge when the dc voltage is decoupled from the output electrode.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: April 20, 2010
    Assignee: Raytheon Company
    Inventors: Istvan Rodriguez, Robert A. Lindquist, Jr.
  • System and method of changing a PWM power spectrum
    Patent number: 7701307
    Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: April 20, 2010
    Assignee: Silicon Laboratories, Inc.
    Inventors: Richard Beale, John Khoury
  • Frequency locking structure applied to phase-locked loops
    Patent number: 7701298
    Abstract: A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: April 20, 2010
    Assignee: Megawin Technology Co., Ltd.
    Inventors: Jyh-Hwang Wang, Wang-Tiao Huang
  • Spread spectrum frequency synthesizer with improved frequency shape by adjusting the length of a standard curve used for spread spectrum modulation
    Patent number: 7701297
    Abstract: A frequency synthesizer is described illustrating a method for modulation having improved frequency shape for spread spectrum modulation. In particular, the a standard curve is generated, wherein the standard curve modulates an input signal to generate a spread spectrum of frequencies with reduced amplitude and spreading of bandwidth. The standard curve is sampled at a sampling frequency. The length of the standard curve is adjusted such that critical points of the standard curve are captured.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: April 20, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventor: Shuliang Li
  • Digital loop filter for all-digital phase-locked loop design
    Patent number: 7696832
    Abstract: A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: April 13, 2010
    Assignee: National Chiao Tung University
    Inventors: Chen-yi Lee, Ching-che Chung
  • Phase locked loop and method for controlling the same
    Patent number: 7696831
    Abstract: Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: April 13, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon
  • Digital controlled oscillator, frequency synthesizer, radio communication apparatus using the same, and control method for the same
    Patent number: 7696830
    Abstract: The digital controlled oscillator includes a variable capacitance section having a first capacitor array of a plurality of first variable capacitors and a second capacitor array of a plurality of second variable capacitors, and generates a signal having an oscillation frequency corresponding to the capacitance value of the variable capacitance section. The first capacitance change amount in the individual first variable capacitors is a value obtained by multiplying the second capacitance change amount in the individual second variable capacitors by an integer equal to or more than 2, and the number of second variable capacitors is equal to or more than a value obtained by subtracting 1 from the integer equal to or more than 2.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Atsushi Ohara, Hisashi Adachi