Abstract: This invention provides a structure and method for interconnecting logic devices through line segments which can be joined by programming antifuses. One of several programming lines can be connected through an interconnect line segment to each terminal of each antifuse in the array. Interconnect line segments connected to opposite terminals of the same antifuse are connected to a different programming line in order to be able to apply different voltages to the two terminals of the antifuse. An addressing structure selectively connects interconnect line segments to their respective programming lines, and programming voltages applied to the programming lines cause a selected antifuse to be programmed. A novel addressing feature sequentially addresses two transistors for the line segments to be connected, and takes advantage of a capacitive pumped decoder to maintain the addressed transistors turned on while programming voltages are applied.

Abstract: A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor.

Abstract: A unitary semiconductor integrated circuit is constructed using a non-threshold logic NTL circuit for a circuit which has a light load or a light load driving capability, using an NTL circuit additionally provided with an emitter-follower output circuit for effecting a circuit having a comparatively heavy load, and using a super pull-down logic (SPL) circuit for effecting a circuit having a heavy load. The NTL circuit thereof which receives an output signal generated by the emitter-follower output circuit or from the SPL circuit associated with a preceding logic gate circuit stage uses, as its operating voltage, the operating voltage of the emitter-follower output circuit or that of the SPL circuit.

Abstract: An Exclusive-Or circuit has a symmetrical arrangement of components in order to provide an identical input impedance for both input signals and to provide identical switching and signal propagation times. The circuit includes input stages (EF.sub.1, EF.sub.2 ; EF.sub.3, EF.sub.4) for receiving first and second input signals (V.sub.E1 ; V.sub.E2) and emitter followers (EF.sub.5, EF.sub.6, EF.sub.7, EF.sub.8) connected to the input stages. A current switch stage (T.sub.11, T.sub.12, T.sub.13, T.sub.14) is driven by the input stage for the first input signal, and an identical current switch stage (T.sub.21, T.sub.22, T.sub.23, T.sub.24) is driven by the input stage for the second input signal. These current switch stages are connected by load resistors (R.sub.1, R.sub.1) to one pole of an operating voltage source (U.sub.B). Another current switch stage (T.sub.15, T.sub.16), is connected between a current source (I.sub.O /2) and the current switch stage (T.sub.11, T.sub.12, T.sub.13, T.sub.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the integrated circuit which is subject to the local condition and produces a response to the local condition which is proportional to the local condition's effect on the active element and a compensation element which is coupled to the detecting element and to the portion for reacting to the response of the detecting element tot he local condition by providing a compensating input to the portion which is proportional to the response and which compensates for the local condition's effect on the active element. An embodiment of the apparatus which compensates for leakage currents in FETs in a dynamic CMOS integrated circuit employs one or more FETs which are interspersed among active FETs as the detecting element and a current mirror as the compensating element.

Abstract: A digital logic circuit having multiple inputs and a product-of-sums output uses multi input OR circuits with interacting constant-current and constant-voltage elements to improve voltage transfer characteristics. A second-level arbitration circuit connects to the OR circuits and provides mutually exclusive pull-up and pull-down control signals as a logical function of the states of the OR circuits. An output stage connects to the arbitration circuit. The output stage comprises pull-up and pull-down drivers responsive to the output of the second-level arbitration circuit. The digital logic circuit operates at high speed because its transistors are prevented from entering saturation. The logic circuit is easily expandable and provides a simple and direct method of implementing logic circuits which provide product-of-sums outputs.

Abstract: A global reset circuit especially suitable for integration into a microprocessor and implemented in CMOS technology is disclosed herein. This circuit includes reset circuitry having an input adapted for connection with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output adapted for connection with at least one circuit component to be reset, for example certain components forming part of a microprocessor. To this end, the circuitry provides a reset signal at its output upon initiation of the power supply voltage and until the power supply voltage reaches a predetermined level, at which time the reset signal is removed. A latching circuit which forms part of the reset circuitry is operated by the power supply voltage in a first state during the presence of the reset signal and in a second, latched state for removing the reset signal.

Abstract: A circuit, which may be included as part of an integrated circuit chip including a microprocessor or other device needing initialization when being powered up, generates a reset signal at a time determined by the voltage rise characteristics of the power supply to the device when either initially turned on to the device or recovering from a voltage dip. A power supply sensing node of the circuit is initially discharged to ground potential in order to eliminate any effect of a charge on the node on the timing of the reset signal, such as might be generated by an ambient electromagnetic field.

Abstract: When testing one circuit block of a device, it is desired to have isolation from the other circuit blocks of the device so as to prevent possible failure of the other circuit blocks. A block isolation buffer includes a circuit for providing predetermined voltage levels at the inputs of the circuit blocks which are not being tested thereby assuring that an undesired input does not appear at the inputs of the non-tested circuit blocks.

Abstract: A tristate driver circuit including a first output transistor for furnishing a first output voltage at an output terminal in the on condition, the first transistor being susceptible to disablement or degraded operation from back biasing in the presence of voltages above a particular level at the output terminal in the off condition, a second output transistor for furnishing a second output voltage at the output terminal in the on condition, apparatus for biasing the first and second transistors to allow operation thereof in the presence of enable signals and to disable operation in the absence of enable signals, and apparatus for eliminating back biasing of the first transistor in the absence of enable signals.

Abstract: A circuit configuration includes first, second and third current impressing devices. First and second bipolar transistors have coupled emitter terminals being connected through the first current impressing device to a first potential, collector terminals carrying output signals and being connected directly or through respective resistors to a second potential, and base terminals. A first field effect transistor has a gate terminal being acted upon by a first input signal, a drain terminal being connected through a further resistor to the second potential, and a source terminal being connected to the base terminal of the first bipolar transistor and through the second current impressing device to the first potential.

Abstract: A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages.

Abstract: A translator circuit 82 and operation thereof is disclosed including a control signal generator 48 and an ECL output buffer circuit 84. Control signal generator 48 includes a CMOS inverter comprising transistors 52 and 54. The CMOS inverter is connected to a bipolar junction transistor (BJT) 70 which is further connected to as BJT 76. BJT 70 provides a voltage control signal, V.sub.CS, to ECL output buffer circuit 84. BJT 76 is connected as a transistor in a differential pair comprising transistors 76 and 86. An ECL output signal, V.sub.OUT, is generated in accordance with the operational state of transistors 76 and 86 and additional circuitry associated therewith.

Abstract: An output buffer provides for additional current sinking or sourcing capability by switching in an additional transistor when the output voltage passes a given level. This allows the output buffer to supply DC current to a load without requiring an excessively large AC drive capability, which could undesirably increase switching noise. In a typical embodiment, an inverter senses when the buffer output voltage reaches its switching threshold (approximately V.sub.DD /2), and turns on the additional transistor after a given delay. For example, a CMOS output buffer driving a TTL load may obtain additional current sinking capability by this technique. On-chip buffers (e.g., bus drivers and clock drivers) can also benefit from this technique.

Abstract: A Bi-CMOS logic circuit includes a Bi-CMOS circuit which is composed of first and second bipolar transistors, first and second resistors, and first and second MOS transistors. An input signal is applied to the gates of the first and second MOS transistors, and an output signal is drawn from a connection node at which the first and second bipolar transistors are connected in series between first and second power sources. A third MOS transistor is connected between the collector and emitter of the first bipolar transistor. The input signal is applied to the gate of the third MOS transistor. In place of or in addition to the third MOS transistor, a fourth MOS transistor is provided which is connected between the collector and emitter of the second bipolar transistor. The third and fourth MOS transistors function to decrease roundings of rising and falling edges of the waveform of the output signal.

Abstract: A pre-driver stage includes two pairs of series-stacked transistors for responding to input stage outputs and provides first and second outputs to an output driver stage. The first output becomes low at a certain delay period after the second output becomes low, and the second output becomes high at a certain delay period after the first output becomes high. Therefore, the turn-off of the active driver transistor is completed before the turn-on of the opposite output transistor, inhibiting an overlap current. In another form, the buffer circuit also uses assist transistors placed near the driver transistors for assisting the opposite driver transistors in turning off.

Abstract: TTL to CMOS level translating buffer circuits incorporate multiple stages with feedback and forward couplings between stages that eliminate static current I.sub.cct when TTL high potential level data signal is applied at the buffer circuit input. The feedback and feed forward couplings maintain and enhance signal propagation speed in the buffer circuits at the same time. TTL to CMOS translating latch circuits and flip-flop circuits similarly incorporate feedback and feed forward circuit couplings to save and retain data signals during latch mode, static mode, and tristate mode operation while at the same time substantially eliminating static high current I.sub.cct. The clock circuit portions for the latch and flip-flop circuits also are arranged in clock circuit configurations that are free of static current I.sub.cct.

Abstract: A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the second I/O port is connected to an I/O port of a second digital circuit operating at a relatively high supply voltage. This channel passes communication signals in each direction between the first and second digital circuit. A latching circuit comprising a P Channel FET is biased by the relatively high voltage supply, has an output connected to the second I/O port, and has a control input.

Abstract: A tri-state output buffer has a signal input terminal, a control terminal and a signal ouput terminal and is controlled by a control signal applied to the control terminal so as to be selectively put in an inactive condition maintaining the signal output terminal in a high impedance condition and in an active condition bringing the signal output terminal either into a high level or into a low level in response to a signal applied to the signal input terminal. The tri-state output buffer comprises a pre-buffer circuit having an input node connected to the signal input terminal, and an output node, and controlled by the control signal applied to the control terminal so as to selectively bring the output node into a high impedance condition or into an active condition assuming either a high level or a low level in response to the signal applied to the signal input terminal.