Abstract: An output buffer circuit, in which a pair of current sources is connected to positive and negative power sources, and a first inverter having input and output terminals, is arranged between the current sources, in which a second inverter having input and output terminals, is connected to the output terminal of the first inverter, the second inverter including at least one of P-channel and N-channel MOSFETs, and a capacitor is connected between the input and output terminals of the second inverter.

Abstract: A low voltage DC one-shot circuit momentarily increases the voltage applied by a NiCad battery pack to the gate of a MOSFET. A charge pump generates a supply voltage to a monostable multivibrator which is manually actuated by a switch to emit an output pulse of fixed amplitude and pulse width. The pulse is passed through a level shift network where it is summed with a bias voltage for application to the gate of the MOSFET.

Abstract: An integrated circuit (10, 22) contains an active bypass (36) that inhibits high-frequency supply-voltage variations caused by interaction of the circuitry elements (28) with the parasitic inductances (L.sub.HE, L.sub.HP, L.sub.LP, and L.sub.LE) associated with the power supply lines (16.sub.H /24.sub.H /26.sub.H /32.sub.H and 16.sub.L /24.sub.L /26.sub.L /32.sub.L) for the circuit. The bypass centers around a transistor (Q.sub.BP) coupled between the supply lines. An activation circuit (38) provides the transistor with a control signal (V.sub.C) to activate the transistor. A sensing capacitor (C.sub.S) provides a capacitive action between the transistor control electrode and one of the supply lines.

Abstract: There is provided a spare column selection circuit comprising a line switching pair arranged between a spare input/output line pair connected to a spare bit line and a normal input/output line pair connected to a normal bit line pair. The line switching pair are driven by an output of a spare column decoder. A normal line pull-up pair are connected to the corresponding normal input/output line so as to be driven by the output of the spare column decoder. An inverter produces a clock signal having an inverted signal phase against a clock from a spare column decoder, and the inverted clock signal connects the spare input/output line pair to the spare bit line pair.

Abstract: A TTL gate (22) includes a current generating circuit (24) comprising an NPN transistor (30) having its base coupled to a diode (24) and its emitter coupled to one of the gate's output transistors (14). Transistor (30) enables diode (24) to deliver a high current of short duration to the output OUT responsive to a low-to-high output transition. The current provides low-to-high output transition while protecting output transistor (14) from damaging currents caused by a short circuit at output OUT.

Abstract: An integrated circuit in complementary circuit technology comprises a substrate bias voltage generator which reverse biases the substrate, into which tubs of opposite conductivity are inserted. The source regions of the field effect transistors arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, the output of the substrate bias voltage generator is connected by way of an electronic switch to a circuit point lying at ground potential, whereby the switch is driven via the output of the substrate bias voltage generator.

Abstract: Electrical circuitry providing a compatible interface between ECL logic level of -1.6 and -0.8 volts and CMOS logic levels of 0 and +5 volts. Voltage sources of -3.7 and +1.3 volts are provided for supplying operating voltages to the CMOS circuitry in order to set the threshold voltage CMOS inverters at -1.2 volts, the threshold voltage of ECL logic circuits.

Abstract: An output buffer circuit includes a prestage circuit which generates a first potential and a second potential (an intermediate voltage) based on the voltage of an input signal. The first potential is higher than the second potential. A final-stage circuit generates an output signal by controlling a current passing therethrough from a power source on the basis of the potential of the input terminal. The output signal is supplied to an ECL circuit through the output terminal. A control circuit generates a control signal during a predetermined time when a change in voltage of the input signal occurs. A bypass circuit sets the potential of the input terminal of the final-stage circuit lower than the second potential and discharging a parasitic capacitance coupled to the input terminal during the predetermined time defined by the control signal supplied from the control circuit when the prestage circuit outputs the second potential in response to a change in voltage of the input signal.

Abstract: A design for a structured scan path circuit incorporating domino logic circuitry is provided. The scan path circuit allows the rapid evaluation of a predetermined logic function, while allowing the use of automatic test pattern generation programs. Each function input signal has its own latch, the equivalent to the master latch in a standard scan flip-flop. The domino function output also has a latch, the equivalent of the slave latch in the scan flip-flop. The use of the input latches eliminates the need to insure the stability of the function input signals during the evaluation of the domino logic function. Thus, the input latches eliminate the potential "hazard" problems which can occur due to the instability of the input signals during evaluation of the domino logic function. A scan enable signal selectively enables and disables the function evaluation by the domino logic circuitry.

Abstract: A pass gate multiplexer receiver integrated circuit on a semiconductor substrate including a pass gate circuit including first and second field effect transistors of opposite polarity for providing an input signal to an output line, the first transistor including a first bipolar transistor for providing clamping an electrostatic discharge protection and the second transistor including a second bipolar transistor for providing clamping and electrostatic discharge protection. A control circuit is connected to the pass gate to control operation. In a second embodiment the pass gate further includes a clamping circuit to provide further clamping and electrostatic discharge protection.

Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A first output voltage sensing switching circuit is coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements. The secondary pulldown transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer first. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown transistor element.

Abstract: An integrated circuit apparatus for changing the phase relationship between at least one clock-phase output and a reference clock is disclosed. The sequence control apparatus is coupled to a waveform synthesizer apparatus producing at least one clock-phase output. The clock-phase output from the waveform synthesizer is looped back to a skew control apparatus. The deskew control apparatus measures the skew between the falling edge of the clock-phase output and the rising edge of the reference clock and generates a control signal to a shifter. The shifter deskews the clock-phase output automatically with respect to the reference clock by shifting an input pattern to a digital-to-time domain converter (DTC). A sampling window circuit in the deskew control apparatus is coupled to the shifter for reducing the skew between the reference clock and the clock-phase output to a small, well-defined amount.

Abstract: A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The push-pull output stage includes complementary output field-effect transistors which are formed by respective first and second groups of parallel-connected subtransistors (P1 to P4; N1 to N4), the subtransistors in each group being of the same conductivity type and opposite from that of the subtransistors in the other group. A resistance element (TP0 to TP3; TN0 to TN3) is connected into the lead to each gate electrode of each of the subtransistors (P1 to P4; N1 to N4) of the two groups of subtransistors. A disconnecting field-effect transistor (PD1 to PD4; ND1 to ND4) is associated with each subtransistor (P1 to P4; N1 to N4) of the two groups of subtransistors.

Abstract: In an output circuit for use in a semiconductor IC comprising a CMOS transistors constituting an output buffer, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element. The transfer gate reduces the changes in the gate potentials of output transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output transistors, is minimized.

Abstract: A semiconductor substrate bias circuit is disclosed which comprises: first and second substrate biasing means connected in parallel between the substrate and a ground node, for pumping the charges from said substrate to said ground node or in the reverse direction in order to bias said substrate; and a detecting means for selectively enabling said first and second substrate biasing means in accordance with the levels of the substrate bias voltage. The circuit of the present invention is capable of supplying adequate bias voltages depending on the various operating modes, reducing the standby current loss at a standby state, and is suitable for being installed on a VLSI semiconductor chip.

Abstract: A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The integrated circuit of which the push-pull output stage is a part is susceptible to high switching speeds in which the pulse-like signal varies between high and low voltage levels. The push-pull output stage inhibits the overshoot of the pulse-like signal leading to inaccurate interpretation of the pulse-like signal as having a high voltage level when the pulse-like signal actually has a low voltage level. The output stage includes output field-effect transistors comprising two groups (12, 14) of parallel-connected subtransistors (TN1 to TNn, TP1 to TPn). The gate zones of the subtransistors in each respective group are connected together. To the gate zones of the subtransistors (TN1 to TNn) of at least one (12) of the two groups (12, 14) a current dissipating or grounding transistor (TS1) is connected.

Abstract: In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node. An optional load device, an optional pull-down device, an optional second capacitor, an optional string of diode-connected devices, and an optional feedback device may be included. Device channel lengths are specified for proper operation. In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor.

Abstract: In a high speed digital computer data transfer system, data bus voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. The output voltages are converted to the proper logic levels with the aid of a differential (sense) amplifier. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Abstract: A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages.

Abstract: A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.