Abstract: A bipolar/CMOS integrated circuit uses an on-chip amplifier to provide an intermediate voltage supply (18) to two groups of small geometry CMOS circuits. Bipolar devices (24) may use a full five volts from the outside supply rails (12, 14).

Abstract: A level shift circuit of the present invention includes an input differential pair of transistors, as an input circuit section, which are switchingly operated in accordance with the level of an input signal supplied from a preceding circuit. An output circuit section is composed of first and second emitter follower transistors. A third transistor has its current path connected at one end to an emitter of the first emitter follower transistor and makes an output level of the first emitter follower transistor at a predetermined level. A fourth transistor has its current path connected at one end to the other end of the reference potential and its gate electrode connected to an output terminal of the second emitter follower transistor and is driven by an output voltage of the second emitter follower transistor to allow an output level of the first emitter follower transistor to be shifted to a low level.

Abstract: The present logic circuit family is derived from the conventional DCCS logic circuit family. The logic circuit shown in the attached drawing is a six-input AND/NAND. It includes: a logic tree (41) comprised of bottom, middle, and top stages (44, 45, 46) cascoded and dotted at the tree output nodes (OUT, OUT) to perform a determined logic function (F, F). The top stage (46) includes a current switch (49) formed by a pair of input transistors (TX431, TX432) connected in a differential amplifier configuration. The base of one input transistor (TX431) on the left side of the tree is connected to the output of an AND gate, which consists of input diodes (D431, D432, . . . ) and resistor (RD41). True (IN PHASE) logic input signals (Z41, Z42, . . . ) are ANDed in this AND gate and a first elementary output signal, is available at the common emitter node (CN43) of the said differential pair. On the right side, additional inpout transistors (TX433, . . .

Abstract: An internal voltage converter in semiconductor integrated circuit, comprises an oscillator, a sub circuit including a buffer and a charge-pumping circuit and a power part, a main circuit including a buffer and a charge-pumping circuit and a power part, and a detector. A plurality of voltage converting stages are composed in parallel to be divided when operating so that the unnecesary consumption of the power is reduced in the case of providing the stand-by power and the stability of the internal power supply voltage is also improved.

Abstract: In one embodiment of the invention, an inverter inverts an input signal and provides this inverted input signal into the base of an NPN bipolar transistor, acting as a pull-up device, whose collector is coupled to a positive power supply voltage. The input signal coupled to the input of the inverter is also coupled to the gate of a large N-channel MOSFET, acting as a pull-down device, having its drain coupled to the emitter of the bipolar transistor and its source coupled to ground. The common node of the bipolar transistor and the N-channel MOSFET provides the output signal of the driver. This driver uses much less area than a standard two-bipolar transistor BiCMOS driver with substantially equal performance. A small P-channel MOSFET having its gate connected to the input signal may be connected across the base and emitter of the bipolar transistor to provide a full output voltage at the output of the driver.

Abstract: According to this invention, there is disclosed a semiconductor integrated circuit apparatus having a programmable logic gate wherein whether an opening for connecting a metal wire in a programming region is present or absent is determined in a manufacturing step by determining the content of a program in the programming region, and the program is performed by determining whether a programming element is connected to the metal wire through the opening or not.

Abstract: A power supply reset circuit with a PNP transistor for detecting saturation of an NPN transistor and resetting a fault latch. The PNP and NPN transistors may be separate, discrete components. A preferred embodiment includes a vertical NPN transistor formed in a semiconductor substrate and includes a base, emitter and collector region. The functional, lateral PNP transistor is also fashioned in the semiconductor substrate and has a base region formed by the collector region of the NPN transistor, an emitter region formed by the base region of the NPN transistor, and a distinct, separate collector region disposed in selected proximity to the base and emitter region of the vertical NPN transistor, forming a saturation detector.

Abstract: An ECL-TTL level converting circuit comprises a first transistor having a collector connected to a ground line and an emitter connected to a negative voltage line through a constant current source, and a second transistor having a collector connected to a positive voltage line through a first resistor and an emitter commonly connected to the emitter of the first transistor. The base of one of the first and second transistors is connected to receive a reference voltage, and the base of the other of the first and second transistors is connected to receive an input signal. A third transistor is connected at its base to the collector of the second transistor and at its collector to the positive voltage line through a second resistor. An emitter of the third transistor is connected to the ground line through a third resistor and also connected to a base of a fourth transistor having an emitter connected to the ground line.

Abstract: An on-chip power supply regulation system for a VLSI circuit such as a dynamic RAM is disclosed. The system includes a high power supply voltage detection circuit and a power supply clamp circuit, where a clamped voltage generated by the clamp circuit biases the functional circuitry when the high power supply voltage detection circuit detects an overvoltage conditions. The bias voltage applied to the functional circuitry in the normal operating condition can be a regulated voltage generated from the power supply voltage. Further included in the disclosed circuit is a burn-in voltage generation circuit and a burn-in voltage detection circuit, which can apply an accelerated voltage which depends upon the applied power supply voltage, when the power supply voltage is higher than during normal operation but lower than in the overvoltage condition enabling the clamp operation.

Abstract: Intermediate path splitting circuit arrangements are coupled between the input node and output stage of an IC defining a plurality of different signal propagation paths. A relatively higher speed output pullup turn on signal progagation path is coupled between the input node and the output pullup transistor element for turning on the output pullup transistor element at relatively higher speed in response to a first input data signal. A relatively slower speed output pulldown turn off signal propagation path turns off the output pulldown transistor element at a relatively slower speed in response to the first data input signal. Similar circuit arrangements are provided for relatively high speed turn on of the pulldown transistor element and relatively low speed turn off of the pullup transistor element. Control of turn on and turn off of the respective output pullup and pulldown transistor elements is from separate output driver nodes for higher speed operation.

Abstract: A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.

Abstract: A NAND gate circuit which can be used for a decoder circuit, includes a high potential voltage source (V.sub.cc), an output terminal (V.sub.OUT), and a load element (T.sub.1) connected between the high potential electric voltage source (V.sub.cc) and the output terminal (V.sub.OUT). A driving circuit is serially connected with the output terminal (V.sub.OUT), and a low potential voltage source (V.sub.ss), and has a plurality of driving transistors (T.sub.2, T.sub.3) which are serially arranged. An input signal is applied to each gate. At least one transistor, constituting the driving circuit, has a driving performance different from the other transistors of the driving circuit. An ideal NAND gate circuit can be provided in which erroneous operation due to noise can be effectively prevented by setting the input threshold voltage to a constant voltage no matter what the combination of the input signals.

Abstract: A CMOS analog integrated circuit comprising a plurality of nodes for simultaneously computing the largest of the signals at inputs of the nodes. There is a common line supplying current and producing a maximum voltage potential and a plurality of nodes connected to the common line. Each node comprises a follower transistor having a source operably connected to the common line for sourcing current and a gate being the input of the node and being connected to a current signal input source providing a current signal to the node to be compared to the current signals at respective ones of the other nodes. There is an inhibitor transistor having a gate connected to the common line and a drain operably connected to the gate of the follower transistor. The inhibitor transistor provides the voltage output of the node and inhibits the voltage output at all nodes connected to the common line which have a current signal which is smaller than the largest current signal connected to one of the nodes.

Abstract: A semiconductor integrated circuit for controlling the substrate potential is disclosed, in which a substrate potential generating circuit is connected to a substrate and can be operated on at least a certain operation voltage level to generate the substrate potential. A detection circuit outputs a first detection signal upon detecting that the substrate potential has become lower than the operation voltage level by more than a preset amount, and outputs a second signal upon detecting that the substrate potential has reached a preset level which is slightly lower than the operation voltage level. A charging circuit charges the substrate upon receiving the first detection signal and interrupts the operation of charging the substrate upon receiving the second detection signal.

Abstract: A circuit providing improved noise immunity for a first transistor including power terminals and a gate, the power terminals being connected to a power supply and to a load, and the gate being connected to receive control pulses from a pulse source for turning the first transistor on and off. A second transistor has power terminals connected across the gate and one power terminal of the first transistor, and a gate connected to a varying voltage circuit. This varying voltage circuit provides a voltage on the gate of the second transistor which varies in proportion to the spacing between the control pulses and turns on the second transistor when the spacing is greater than a preset value. The pulse source charges the varying voltage circuit during normal operation and the charge turns off the second transistor.

Abstract: An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.

Abstract: In a threshold logic circuit, digital input signals are weighted and summed up and then the sum of weighted digital signals is compared with a threshold value. The threshold logic circuit comprises a plurality of current switching circuits and means for summing up the output currents from the current switching circuit. The weights for the input signals are changed by controlling supply currents to the current switching circuits.

Abstract: A low voltage DC one-shot circuit momentarily increases the voltage applied by a NiCad battery pack to the gate of a MOSFET. A charge pump generates a supply voltage to a monostable multivibrator which is manually actuated by a switch to emit an output pulse of fixed amplitude and pulse width. The pulse is passed through a level shift network where it is summed with a bias voltage for application to the gate of the MOSFET.

Abstract: A circuit for predriving a signal conductor includes a logic circuit/level sensing control mechanism that prevents the simultaneous condition of switching devices through which the signal conductor is coupled to respective predrive voltage sources, thereby avoiding the establishment of a current path from a power supply source to ground. First and second controlled current flow paths are provided by way of first and second switching transistor circuits, that are coupled between first and second voltage reference sources, corresponding to first and second logic levels, respectively, and the signal conductor to be driven. To predrive the conductor, the current flow path through one of the transistor circuits is gated on, while the current flow path through the other transistor circuit is interrupted. At the same time the flow of current between the other voltage source and the signal conductor is inhibited, as the signal conductor is brought to an intermediate voltage level.

Abstract: A sense amplifier with two input control stages whose input voltages are equalized during a precharge cycle by a switching means.