Abstract: A high speed, high density, low power dissipation all parallel FET logic circuit includes a driving stage having a plurality of parallel FETs of a first conductivity type for receiving logic input signals and a load FET of second conductivity type connected to the common output of the driving stage. A complementary FET inverter including serially connected FETs of first and second conductivity type is connected to the common output and the load FET. According to the invention the voltage transfer function of the complementary inverter is skewed so that the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the first conductivity type is made substantially greater than the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the second conductivity type. By skewing the voltage transfer function of the complementary inverter the voltage lift-off interval is dramatically decreased, thereby improving the speed.

Abstract: A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

Abstract: An integrated circuit input buffer is adapted to operate at either of two input levels, typically either TTL or CMOS logic levels. This is accommplished by switching an additional transistor (e.g. 15) into a path between the output node (e.g. 12) and a power supply voltage (e.g. V.sub.DD), thereby changing the ratio of the pull-up to pull-down devices. The desired input level may be selected after the manufacture of the device, as by applying a voltage to a package terminal, or by programming a register during operation of the integrated circuit.

Abstract: CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit is connected by parallel N channel and P channel devices to serially connected N and P channel devices. The serially connected N and P channel devices are connected across a CMOS power supply with gate connections connected to the logic circuit. The parallel devices provide a regulating feedback current to one of the serially connected P channel and N channel devices during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices. The voltage at the junction of the serially connected P and N channel devices is regulated by each of the parallel connected devices.

Abstract: In a data processing system having an ALU and a memory, a decode/driver circuit has a dynamic node in which the voltage variation of the node is controlled. When the circuit is enabled, the dynamic node is precharged to a predetermined voltage potential which drives an output drive transistor. The output drive transistor couples a decoded select signal to an output terminal and inadvertently causes the dynamic node's voltage potential to change, thereby negatively affecting the voltage at the output terminal. To compensate, a transistor is provided which connects a predetermined voltage terminal to the dynamic node in response to the voltage at the output terminal.

Abstract: An integrated circuit for level shift is a parallel-connected circuit comprised of a first circuit including a first MOS FET of one conductive type, a third MOS FET of another conductive type and a first MOS FET of the other conductive type which are series-connected in this order and a second circuit including a second MOS FET of the one conductive type, a fourth MOS FET of the other conductive type and a second MOS FET of the other conductive type which are series-connected in this order, wherein gates of the first and second MOS FETs of the one conductive type are connected respectively to the output side and input side of an inverter connected to a low voltage electric power source, gates of the third and fourth MOS FETs of the other conductive type both are connected to a reference voltage source, a gate of the first MOS FET of the other conductive type is connected to a common junction point of the fourth MOS FET and the second MOS FET of the other conductive type, a gate of the second MOS FET of the ot

Abstract: A semiconductor integrated circuit includes: a data output terminal; a first semiconductor element connected between a first operating potential point and the data output terminal; a second semiconductor element connected between the data output terminal and a second operating potential point; first control means connected to a control input terminal of the first semiconductor element; second control means connected to a control input terminal of the second semiconductor element; first generating means for generating a first predetermined voltage; and second generating means for generating a second predetermined voltage higher than the first predetermined voltage.

Abstract: An integrated circuit obtains improved protection of output buffers against damage from electrostatic discharge (ESD). Each output buffer is connected to its bondpad by means of a resistor, and protective clamping diodes are disposed around the periphery of the bondpad. It has been found that a suitably sized resistor allows the protective diodes to discharge an ESD event before damage to the buffer occurs, by reducing current flow through the buffer, without significantly limiting performance.

Abstract: An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region.

Abstract: A TTL to CMOS buffer includes a PMOS transistor and an NMOS transistor connected in series between Vcc and Vss. The buffer input is applied to the gate of both the PMOS and the NMOS transistor, and the buffer output is provided from the point of connection between the PMOS and the NMOS transistor. At least one other PMOS transistor has one current electrode connected to Vcc and a current electrode connected by a switch to the point of connection between the first PMOS and the NMOS transistor. At least one NMOS transistor has one current electrode connected to VSS and a current electrode connected by another switch to the point of connection between the first PMOS and the first NMOS transistor. Each switch is controlled by respective control signal generated by a temperature detecting circuit; each control signal is indicative of whether the device temperature is above or below a different predetermined level.

Abstract: A high performance latch circuit having complemented isolation means that selectively maintain the state of the latch at a given logic state or input a new logic state thereto. The latch is made up of several legs of series connected translators, the legs being connected in parallel. Selective gating is provided by the transistors directly coupled to the output node.

Abstract: A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from subsequent logic stages. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting part of the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

Abstract: A semiconductor integrated circuit device for setting operational functions dependent on connection of a first bonding pad (20) to a power supply includes switching transistors (Q11, Q40, Q52, Q32) for resetting an input signal line (30) connected to the first bonding pad to a predetermined potential when there is no power supply potential applied to the first bonding pad immediately after turn-on of an operation power supply, at least one inverter (Q3, Q4, Q13, Q14; Q42, Q43; Q50, Q51) responsive to the turn-on of the power supply for the device, for setting and maintaining the potential on the input signal line, and switching transistors (Q12; Q32; Q41; Q52) to be turned on in response to output of the inverter, for cutting off a current path from the power supply through the bonding pad to the input signal line.

Abstract: A BiCMOS logic circuit includes a MOS logic circuit connected between a high voltage supply line and a low voltage supply line and having an input connected to an input terminal, and an output circuit composed of first and second bipolar transistors connected in series between the high and low voltage supply lines. The first bipolar transistor has a base connected to an output of the MOS logic circuit, and a connection node of the first and second bipolar transistors is connected to an output terminal. In addition, a base current supplying circuit having first and second MOS transistors is connected in series between the first voltage supply line and a base of the second bipolar transistor. The first MOS transistor has a gate connected to the output of the MOS logic circuit, and the second MOS transistor has a gate connected to the input terminal.

Abstract: A circuit for generating a reset signal on chip power-up includes two field effect devices connected between a power supply voltage and the input to an inverter. A capacitor is connected between the inverter input and the low supply voltage. Current flows through the field effect devices to charge the transistor only when the supply voltages are greater than the sum of the absolute values of their threshold voltages. The output of the inverter is used as the chip power-up reset signal.

Abstract: A semiconductor integrated circuit comprises a first input circuit for generating an internal chip enable signal in response to a chip enable signal externally applied; and a second input circuit for supplying to an internal circuit a signal corresponding to a data signal externally applied thereto, the second input circuit containing a gate circuit controlled by an internal chip enable signal. The gate circuit responds to the data signal at a first response speed, and responds to the internal chip enable signal at a second response speed when the semiconductor integrated circuit is changed from the active state to the stand-by state. The second response speed being slower than the first response speed, so as to prevent the semi-conductor integrated circuit from being set into the stand-by state by a false operation of the first input circuit.

Abstract: An integrated circuit is formed in a semiconductor chip and connected to at least a first source of voltage and at least a second source of voltage, negative with respect to the first source of voltage. A number of integrated circuit components are activated by the first and second sources of voltage and are interconnected to provide desired functions. An integrated circuit capacitive element in the form of the gate capacitance of a field effect transistor and in the form of a reversed biased diode is connected between the first and second sources of voltage to decouple integrated circuit inherent inductance in series with the first and second sources of voltage.

Abstract: An active dummy load substantially reduces skews for input signals of a CML or an ECL series gate by generating a selectable capacitance that adjusts the delay time of the output signal in relation to the changing of the input signal to one of two states.

Abstract: The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).

Abstract: A sense circuit includes first and second input nodes, first and second output nodes, first to fifth MOSFETs of N-channel type, and first and second potential setting circuits, and the first and second output nodes are precharged to a power source potential by the first and second potential setting circuits before the sensing operation is started. After this, the first MOSFET is turned on by a control signal to start the sensing operation. After the sensing operation is started, the potentials of the first and second input nodes are respectively amplified by the second and third MOSFETs and the fourth and fifth MOSFETs and the amplified potentials are derived from the first and second output nodes.