Abstract: The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

Abstract: A display device includes a substrate including a bending area, a display area. A plurality of first wires is disposed above the substrate. A second wire is disposed above the plurality of first wires. A third wire is disposed above the second wire. At least a portion of the second wire and at least a portion of the third wire are disposed in the bending area.

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include depositing a second metal on a first metal without protecting the dielectric, protecting the metal with a cross-linked self-assembled monolayer and depositing a second dielectric on the first dielectric while the metal is protected.

Abstract: There is provided an electronic component-embedded board. The electronic component-embedded board includes: a first insulating layer; a metal layer formed on the first insulating layer; a first electronic component disposed on the metal layer; a second insulating layer formed on the first insulating layer and the metal layer such that the first electronic component is buried in the second insulating layer; a second electronic component disposed above the second insulating layer; and a heat radiating member thermally connected to the metal layer exposed from the second insulating layer and thermally connected to the second electronic component.

Abstract: The present invention relates to an adhesive resin composition for a semiconductor, including: a (meth)acrylate-based resin including a (meth)acrylate-based repeating unit containing an epoxy-based functional group and a (meth)acrylate-based repeating unit containing an aromatic functional group, the (meth)acrylate-based resin having a hydroxyl equivalent weight of 0.15 eq/kg or less; a curing agent including a phenol resin having a softening point of 100° C. or higher; and an epoxy resin, wherein the content of a (meth)acrylate-based functional group containing an aromatic functional group in the (meth)acrylate-based resin is 2 to 40% by weight, an adhesive film for a semiconductor including the above adhesive resin composition for a semiconductor, a dicing die bonding film including an adhesive layer including the adhesive film for a semiconductor, and a method for dicing a semiconductor wafer using the dicing die bonding film.

Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.

Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.

Abstract: A deposition mask capable of performing high-definition patterning while suppressing position gap between a substrate for vapor deposition and an opening arrangement of the deposition mask during vapor deposition and a manufacturing method thereof are provided. A deposition mask (1) includes a resin film (2) having an opening (4) pattern for forming a thin layer pattern by vapor deposition on a substrate for vapor deposition. The deposition mask (1) includes a low-emissivity layer (5) whose emissivity is lower than that of the resin film (2), which is formed at least partly on a surface of the resin film (2) facing a vapor deposition source, thereby suppressing temperature rise of the resin film (2) due to heat radiated from the vapor deposition source.

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

Abstract: Provided are a flip chip laser bonding apparatus and a flip chip laser bonding method, and more particularly, to an apparatus and method for flip chip laser bonding, in which a semiconductor chip in a flip chip form is bonded to a substrate by using a laser beam. According to the flip chip laser bonding apparatus and the flip chip laser bonding method, even a semiconductor chip that is bent or is likely to bend may also be bonded to a substrate without contact failure of solder bumps by bonding the semiconductor chip to the substrate by laser bonding while pressurizing the semiconductor chip.

Abstract: A light emitting device includes a light emitting element, a covering member and a metal layer. The light emitting element includes a semiconductor layer having a main light emission surface and an electrode formation surface on an opposite side of the main light emission surface, and a pair of electrodes disposed on the electrode formation surface. The covering member covers a side surface of the light emitting element. An outer surface of the covering member defines a recess. The metal layer is connected to the pair of electrodes. The metal layer is arranged in the recess.

Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber.

Abstract: Provided are a semiconductor chip bonding apparatus and a semiconductor chip bonding method, and more particularly, to an apparatus and method of bonding a semiconductor chip to an upper surface of a substrate or another semiconductor chip. According to the semiconductor chip bonding apparatus and the semiconductor chip bonding method, productivity may be increased by quickly and accurately bonding a semiconductor chip to a substrate or another semiconductor chip.

Abstract: A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.