Abstract: A wafer processing method includes a liquid supplying step of supplying a liquid to the front side of a wafer, a close contact making step of pressing a protective film against the front side of the wafer with the liquid interposed therebetween, thereby bringing the protective film into close contact with the front side of the wafer, a protective member fixing step of covering the protective film, with a protective member formed from a liquid resin curable by external stimulus, thereby fixing the protective member through the protective film to the front side of the wafer, a grinding step of grinding the back side of the wafer to reduce the thickness of the wafer, and a peeling step of peeling the protective film and the protective member from the wafer thinned by the grinding step.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.

Abstract: Embodiments of the inventive concepts provide a method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer. The method includes preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition includes a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %, quaternary ammonium salt, and primary amine.

Abstract: There is provided a light source device which includes at least one kind of light emitting elements of which the number is one or more, and a phosphor excited by output light of the light emitting element. In a case where all light emitting elements mounted before the phosphor is mounted in the light source device emit light, the light source device has a peak wavelength of output light in a first wavelength region of longer than 440 nm and 490 nm or shorter, and has a peak wavelength of output light in a second wavelength region of 380 nm to 440 nm. Thus, it is possible to provide a light source device which can cause the white color, the dark-blue color, and the black color to simultaneously look vivid when an irradiation target (for example, clothes or the like) is irradiated.

Abstract: A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.

Abstract: A display panel comprises an array substrate, an opposing substrate, a liquid crystal layer and a sealing member. An array substrate comprises a substrate, a switch array structure formed on the substrate, a retaining wall structure disposed on the peripheral region of the substrate and substantially surrounding the switch array structure, and a flow guiding structure disposed on an area surrounding the peripheral region between the switch array structure and the retaining wall structure and having a height different from a height of the retaining wall structure. The opposing substrate is disposed opposing to the array substrate, and the liquid crystal layer is interposed between the array substrate and the opposing substrate, and the sealing member is disposed on the array substrate corresponding to the location surrounding the periphery of the liquid crystal layer and seals the array substrate and the opposing substrate.

Abstract: A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die.

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.

Abstract: A polishing method including polishing to polish a surface of a wafer by sliding the wafer held by a polishing head on a surface of a polishing pad while supplying a polishing slurry to the polishing pad attached to a turntable, the method including correlation derivation to obtain a correlation between a surface temperature of the polishing pad and a haze level of a wafer polished with the use of the polishing pad in advance before performing the polishing, and also the wafer is polished in the polishing while controlling the surface temperature of the polishing pad based on the correlation between the surface temperature of the polishing pad and the haze level of the wafer polished with the use of the polishing pad. Consequently, the polishing method can control a haze in polishing a wafer and thereby prolong the service life of the polishing pad.

Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. The method involves patterning a chemical template material with patterned portions separated by a center to center distance that is substantially equal to a natural period of a block copolymer. A block copolymer material is then deposited and annealed to form self assembled cylinders that are located over the patterned regions of the chemical template and also over areas between the patterned regions. The chemical template layer can be patterned by depositing a first, preliminary block copolymer, over a mask structure and annealing the mask structure to form cylinders in the openings in the mask structure. The cylinders can be removed leaving openings, and a UV exposure can be performed to expose and treat portions of the chemical template layer that are exposed through the opening.

Abstract: Methods of the disclosure include a BN ALD process at low temperatures using a reactive nitrogen precursor, such as thermal N2H4, and a boron containing precursor, which allows for the deposition of ultra thin (less than 5 nm) films with precise thickness and composition control. Methods are self-limiting and provide saturating atomic layer deposition (ALD) of a boron nitride (BN) layer on various semiconductors and metallic substrates.

Abstract: The present disclosure provides a method for manufacturing a thin film transistor comprising, forming a pattern of an active layer on a substrate through a patterning process; performing ion doping to a channel region of the active layer; forming a gate insulating layer; forming a pattern of a gate through the patterning process; performing ion doping to a source contact region and a drain contact region of the active layer; forming an interlayer insulating layer; and performing laser annealing to the active layer, so as to make the active layer crystallize and the ions doped in the channel region, the source contact region and the drain contact region of the active layer activate simultaneously. In this method, the crystallization of the active layer and the activation of the ions doped in the active layer are implemented in the same process, which reduces the process cost and improves the efficiency.

Abstract: A photodetector includes a detector material having an upper layer, a lower layer, and at least one sidewall. Also included as part of the photodetector are a first contact electrically coupled to the detector material through the upper layer and a second contact electrically coupled to the detector material through the lower layer. Diffused into the sidewall by a passivation process is a dopant material operable to electrically isolate the first contact from the second contact via the sidewall. The dopant material is provided by a passivation layer deposited on the sidewall.

Abstract: A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.

Abstract: Disclosed herein in a method of forming a metal oxide film, which can provide a high-quality metal oxide film while enhancing production efficiency. The method includes the steps of: turning a raw-material solution having a metallic element into a mist, to obtain a raw-material solution mist; turning a reaction aiding solution into a mist, to obtain an aiding-agent mist; feeding the raw-material solution mist and the aiding-agent mist into a mixing vessel, thereby mixing the raw-material solution mist and the aiding-agent mist, to obtain a mixed mist; and feeding the mixed mist onto a back surface of a substrate which is heated, to obtain a metal oxide film.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

Abstract: Light emitting diodes, components, and related methods, with improved performance over existing light emitting diodes. In some embodiments light emitter devices included herein include a submount, a light emitter, a light affecting material, and a wavelength conversion component. Wavelength conversion components provided herein include a transparent substrate having an upper surface and a lower surface, and a phosphor compound disposed on the upper surface or lower surface, wherein the wavelength conversion component is configured to alter a wavelength of a light emitted from a light source when positioned proximate to the light source.

Abstract: A silicon film forming method of forming a silicon film in a recess with respect to a target substrate having on its surface an insulating film in which the recess is formed. The method includes (a) forming a first silicon film filling the recess by supplying a Silicon raw material gas onto the target substrate, (b) subsequently, etching the first silicon film by supplying a halogen-containing etching gas onto the target substrate such that surfaces of the insulating film on the target substrate and on an upper portion of an inner wall of the recess are exposed and such that the first silicon film remains in a bottom portion of the recess, and (c) subsequently, growing a second silicon film in a bottom-up growth manner on the first silicon film that remains in the recess by supplying a Silicon raw material gas onto the target substrate after the etching.

Abstract: The present disclosure provides a LED package structure and a LED light-emitting device. The LED package structure comprises a LED chip and a wavelength converting layer covering the LED chip. The wavelength converting layer contains red phosphor, which has lower amount in edge portion than in center portion. It is possible to avoid direct or indirect excitation for generating red light in edge portion of the LED chip by adjusting the amount of red phosphor in edge portion to be lower, so that the color temperature in edge portion may be adjusted toward to high color temperature, and thus the phenomenon of yellow halo may be alleviated.

Abstract: An ion implantation method includes measuring a beam energy of an ion beam that is generated by a high-energy multistage linear acceleration unit operating in accordance with a tentative high-frequency parameter, adjusting a value of the high-frequency parameter based on the measured beam energy, and performing ion implantation by using the ion beam generated by the high-energy multistage linear acceleration unit operating in accordance with the adjusted high-frequency parameter. The tentative high-frequency parameter provides a value different from a value of the high-frequency parameter for achieving a maximum acceleration in design to a high-frequency resonator in a part of stages including at least a most downstream stage. The adjusting includes changing at least one of a voltage amplitude and a phase set for the high-frequency resonator in the part including the at least most downstream stage.