Abstract: The present disclosure relates to a device and method for forming efficient quantum devices, in particular quantum devices that have not been contaminated in ex-situ processes. In particular the presently disclosed method can be applied for manufacturing of a Josephson junction which is an element in a tunable superconducting qubit.

Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

Abstract: An apparatus includes a lead frame, a dam and adhesive on portions of the lead frame, and an integrated circuit die having a portion on the dam and another portion on the adhesive. The lead frame can include two portions, or two lead frames. The dam can bridge a space between the two lead frames. The dam can be smaller than the integrated circuit die in at least a width dimension of the dam relative to a width dimension of the integrated circuit die, providing that the integrated circuit die overhangs the dam on each side of the width dimension of the dam. Adhesive is located between the integrated circuit die and each lead frame, adjacent to and on each side of the dam. The dam prevents adhesive from spreading into the space between the lead frames.

Abstract: The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

Abstract: A vapor deposition mask preparation body in which a metal mask is provided on one surface of a resin plate for obtaining a resin mask, and a protective sheet with peel strength not less than about 0.0004 N/10 mm and less than about 0.2 N/10 mm in conformity with JIS Z-0237:2009 is provided on the other surface of the resin plate is prepared, with respect to the vapor deposition mask preparation body, the resin plate is irradiated with laser light from the metal mask side to form a resin mask opening corresponding to a pattern to be produced by vapor deposition in the resin plate, and the protective sheet is peeled off from the resin mask in which the resin mask opening corresponding to the pattern to be produced by vapor deposition is formed.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is famed. Density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

Abstract: A wafer processing method uses a chuck table with smaller diameter than a semiconductor wafer to be processed. A cut through edge trimming is therefore implemented on the periphery of the semiconductor wafer to form a cut through straight side at the periphery and also form a flat portion at the periphery as a positioning means for taping and backside grind processes.

Abstract: A method of arranging a plurality of semiconductor structural elements on a carrier includes arranging at least some of the semiconductor structural elements in multiple groups G and at least one semiconductor structural element of a group G has a property E that determines the position of the respective group G of semiconductor structural elements on the carrier.

Abstract: A method of reducing silicon consumption of a silicon material. The method comprises cleaning a silicon material and subjecting the cleaned silicon material to a vacuum anneal at a temperature below a melting point of silicon and under vacuum conditions. The silicon material is subjected to additional process acts without substantially removing silicon of the silicon material. Additional methods of forming a semiconductor structure and forming isolation structures are also disclosed.

Abstract: A method of forming a semiconductor device includes following steps. First of all, a substrate is provided, and a stacked structure is formed on the substrate. Then, a patterned silicon-containing mask layer is formed on the stacked structure, and the stacked structure is partially removed through the patterned silicon-containing mask layer, to form plural openings in the stacked structure. Following these, a bromine covering process is performed, to form a bromide layer on a portion of the patterned silicon-containing mask layer, and a bromide sublimation process is then performed, to completely remove the bromide layer.

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.

Abstract: The present invention is intended to provide a light-emitting diode (LED) structure which can be easily transferred onto another substrate, a transfer assembly whose adhesive strength with LED structures can be maintained in spite of repetitive transfer processes, LED structures and a transfer assembly for selectively transferring the LED structures, and a transfer method using the same.

Abstract: A the organic EL display 1 includes: a first substrate 10; an organic EL element 4 provided above the first substrate 10; and a multilayer sealing film 2 provided above the first substrate 10 to cover the organic EL element 4, and including a barrier layer and a buffer layer lower in hardness than the barrier layer. The organic EL element covered with the multi layer sealing film includes a protrusion, and a relationship (d/h)<2 holds where h is a height of the protrusion directly below the buffer layer and d is a thickness of the buffer layer.

Abstract: Methods of wordline separation in semiconductor devices (e.g., 3D-NAND) are described. A metal film is deposited in the wordlines and on the surface of a stack of spaced oxide layers. The metal film is removed by high temperature oxidation and etching of the oxide or low temperature atomic layer etching by oxidizing the surface and etching the oxide in a monolayer fashion. After removal of the metal overburden, the wordlines are filled with the metal film.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include depositing a second metal on a first metal without protecting the dielectric, protecting the metal with a cross-linked self-assembled monolayer and depositing a second dielectric on the first dielectric while the metal is protected.

Abstract: A method for recovering a degraded solar cell is disclosed. The method comprises radiating an ultraviolet (UV) light on the degraded solar cell for a period of time in a range from 30 seconds to 5 minutes.

Abstract: The present invention provides a display panel and display device. The display panel includes an array substrate and a color film substrate. The array substrate is provided with a plurality of data lines, a plurality of gate line sets arranged parallel to each other, and a plurality of first thin film transistors. Each set of the gate lines includes a first gate line and a second gate line. gate electrode of each of the first thin film transistors connected to the first gate line correspondingly, and source electrode of each of the first thin film transistors connected to the second gate line correspondingly, and drain electrode of each of the first thin film transistors connected to a first common electrode.