Patents Examined by David X Yi
  • Patent number: 10048886
    Abstract: A method of providing a file system for an electronic device includes organizing a plurality of Non-Volatile Dual In-Line Memory Module-Ps (NVDIMM-Ps) of a memory device of the electronic device into a plurality of groups based on location information of the NVDIMM-Ps, and creating a single File System Instance (FSI) for each group included in the plurality of groups.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 14, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Vishak Guddekoppa
  • Patent number: 10037140
    Abstract: A method includes a processing module of a storage unit of a dispersed storage network (DSN) monitoring input/output (IO) rates of a plurality of disk drives, where access requests for encoded data slices occur at varying rates. The method continues with the processing module determining that the IO rate of a disk drive is exceeding a desired maximum IO rate and identifying a pending access request for an encoded data slice stored in the disk drive. The method continues with the processing module evaluating disk drive processing rates of other storage units that are storing other encoded data slices of a set of encoded data slices that includes the encoded data slice to determine whether the encoded data slice is needed to satisfy the pending access request. When the encoded data slice is needed, the method continues with the processing module migrating the encoded data slice to another disk drive.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Baptist, Joseph Martin Kaczmarek
  • Patent number: 10037159
    Abstract: A memory system includes a memory device including a plurality of blocks and a plurality of page buffers which respectively correspond to the blocks, wherein each of the blocks includes a plurality of pages in which data is stored, and a controller suitable for backing up data, which is stored in a memory included in the controller, in the page buffers when an operation mode is about to change to a power save mode.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 31, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Jae Shin, Jong-Ju Park, Young-Jin Park
  • Patent number: 10019168
    Abstract: In general, the technology relates to a method and system for writing data to persistent storage. More specifically, embodiments of the technology relate to writing data to vaulted memory segments in persistent storage using pre-defined multicast address groups. Further, embodiments of the technology take into account the current state of the persistent storage in order to select the vaulted memory segments in which to store the data.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 10, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael W. Shapiro, Mikhail Orel
  • Patent number: 10013171
    Abstract: A method for reducing stress on a RAID under rebuild is disclosed herein. In one embodiment, such a method includes performing the following actions while the RAID is undergoing a rebuild process: (1) redirect writes intended for the RAID to a temporary storage area located on a same primary storage system as the RAID, and (2) redirect reads intended for the RAID to a secondary storage system configured to store a copy of data in the RAID. The method is further configured to perform the following actions upon completing the rebuild process: (3) update the rebuilt RAID to reflect writes made to the temporary storage area during the rebuild process, and (4) redirect reads and writes to the rebuilt RAID. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Herve G. P. Andre, Rashmi Chandra, Glynis G. Dsouza, Larry Juarez, Tony Leung, Igor Popov, Jacob L. Sheppard, Todd C. Sorenson
  • Patent number: 10013356
    Abstract: The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor is generating the stream of data accesses, the system examines a sequence of strides associated with the stream of data accesses. Next, upon detecting a pattern having a single constant stride in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the single constant stride. Similarly, upon detecting a recurring pattern having two or more different strides in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the recurring pattern having two or more different strides.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 3, 2018
    Assignee: ORACLE INTERNAIONAL CORPORATION
    Inventor: Yuan C. Chou
  • Patent number: 10007523
    Abstract: In a decode stage of hardware processor pipeline, one particular instruction of a plurality of instructions is decoded. It is determined that the particular instruction requires a memory access. Responsive to such determination, it is predicted whether the memory access will result in a cache miss. The predicting in turn includes accessing one of a plurality of entries in a pattern history table stored as a hardware table in the decode stage. The accessing is based, at least in part, upon at least a most recent entry in a global history buffer. The pattern history table stores a plurality of predictions. The global history buffer stores actual results of previous memory accesses as one of cache hits and cache misses.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vijayalakshmi Srinivasan, Brian R. Prasky
  • Patent number: 10001925
    Abstract: A method for setting a compression ratio for utilizing a compressed memory pool (which is backed by pinned memory) by a virtual memory manager (VMM). Compression of pages of corresponding segments can be tracked as part of a VMM paging algorithm that compresses pages to store in a compressed memory pool. A segment having pages with an average compression ratio below a threshold is identified. The identified segment pages are prevented from utilizing the compressed memory pool resulting in optimizing the use of the compressed memory pool.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Sreenivas Makineedi
  • Patent number: 10001938
    Abstract: In accordance with embodiments of the present disclosure, a method may include receiving requirements for building a virtual storage resource from an array of physical storage resources, receiving performance metrics and power metrics of the physical storage resources of the array available for inclusion in the virtual storage resource, determining a plurality of unique combinations of the available physical storage resources that could be used to build the virtual storage resource, determining an effective performance, an effective performance penalty, a total power consumption, and an effective power penalty for each of the plurality of unique combinations, and selecting a single combination of the plurality of unique combinations for the virtual storage resource based on effective performances, effective performance penalties, total power consumptions, and effective power penalties of the plurality of unique combinations.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 19, 2018
    Assignee: Dell Products L.P.
    Inventors: Kanaka Charyulu B, Deepu Syam Sreedhar M, Sandeep Agarwal, Gary E. Billingsley, Abhijit Rajkumar Khande
  • Patent number: 9996288
    Abstract: In one embodiment, a system includes a disk cache that includes a plurality of hard disk drives (HDDs) and a controller. The controller is configured to create one or more tape-managed partitions in the disk cache, each of the one or more tape-managed partitions being configured to store data that is subject to hierarchical storage management (HSM). The controller is also configured to create a premigration queue configured to service premigration data for all of the one or more tape-managed partitions. Moreover, the controller is configured to receive a premigration delay value for a first tape-managed partition, the premigration delay value defining a time period that elapses prior to queuing the premigration data for the first tape-managed partition to the premigration queue. The premigration delay value is based on a volume creation time. Other systems, methods, and computer program products are described in accordance with more embodiments.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, Katsuyoshi Katori, Koichi Masuda, Joseph M. Swingler
  • Patent number: 9990246
    Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 5, 2018
    Assignee: INTEL CORPORATION
    Inventors: Bill Nale, Murugasamy K. Nachimuthu, Jun Zhu, Tuan M. Quach
  • Patent number: 9983893
    Abstract: When a guest of a virtual machine attempts to accesses an address that causes an exit from the guest to the hypervisor of a host, the hypervisor receives an indication of an exit by a guest to the hypervisor. The received address is associated with a memory-mapped input-output (MMIO) instruction. The hypervisor determines, based on the received indication, that the exit is associated with the memory-mapped input-output (MMIO) instruction. The hypervisor identifies the address that caused the exit as a fast access address. The hypervisor identifies one or more memory locations associated with the fast access address, where the one or more memory locations store information associated with the MMIO instruction. The hypervisor identifies the MMIO instruction based on the stored information. The hypervisor executes the MMIO instruction on behalf of the guest.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 29, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Gleb Natapov
  • Patent number: 9983824
    Abstract: A data mirroring control apparatus includes a command distributing unit configured to transmit a first write command to a plurality of mirroring storage devices, the first write command including an instruction for data requested by a host to be written; and a memory lock setting unit configured to set a memory lock on the data requested by the host to be written among data stored in a host memory and configured to release the memory lock on the data after the data with the memory lock is written to the plurality of mirroring storage devices.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju-Pyung Lee
  • Patent number: 9965403
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Patent number: 9959177
    Abstract: A processing device generates a live snapshot of a virtual disk image attached to a virtual machine, wherein generating the live snapshot comprises converting an existing read-write volume to a read-only volume. The processing device generates, from the read-only volume, a temporary snapshot of the virtual disk image, the temporary snapshot comprising a temporary read-write volume. The processing device attaches the temporary snapshot of the virtual disk image to a backup component and causes at least one of the backup component or a backup service to backup the virtual disk image from the attached temporary snapshot.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 1, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Federico Simoncelli, Liron Aravot
  • Patent number: 9959045
    Abstract: In one general embodiment, a tape drive system includes: a read channel; a write channel; logic configured to receiving a request for a write operation to be performed in a tape drive; logic configured to determine an optimum a write procedure in response to receiving the request, the determining being based on expected writing times of each of a plurality of write procedures and an expected transaction size of a next write operation; and logic configured to invoke the determined optimum write procedure in response to determining the optimum write procedure.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James M. Karp, Takashi Katagiri, Yuhko Mori, Yutaka Oishi
  • Patent number: 9959048
    Abstract: Disclosed aspects include management of a set of blocks in a storage system. A set of write requests is initiated to the set of blocks. In response to the set of write requests, a set of expiration metadata for the set of blocks is established. Based on the set of expiration metadata, an expiration event is detected. In response to detecting the expiration event, an expiration operation on the set of blocks is processed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 1, 2018
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Bish, Nikhil Khandelwal, Gregory E. McBride, David C. Reed, Richard A. Welp
  • Patent number: 9952783
    Abstract: A data processing method and apparatus, and a shared storage device, where the method includes receiving, by a shared storage device, a copy-on-write request sent by another storage device, where the copy-on-write request includes data on which copy-on-write is to be performed and a logical unit identifier and snapshot time point of the data; storing the data; and searching, according to the logical unit identifier and snapshot time point of the data, a preset shared mapping table for a corresponding entry, and storing, in the corresponding entry, mapping entry information of the data, where the mapping entry information includes the logical unit identifier and snapshot time point of the data and a storage address that is of the data and in the shared storage device, which can improve efficiency of snapshot data processing.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: April 24, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Cheng Lu, Bin Yang, Ye Zou
  • Patent number: 9952999
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage cache memory in multi-cache environments. A disclosed apparatus includes a remote cache manager to identify a remote cache memory communicatively connected to a bus, a delegation manager to constrain the remote cache memory to share data with a host cache memory via the bus, and a lock manager to synchronize the host cache memory and the remote cache memory with a common lock state.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Shiow-Wen Cheng, Robert Joseph Woodruff
  • Patent number: 9952978
    Abstract: Systems, methods and or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: April 24, 2018
    Assignee: SANDISK TECHNOLOGIES, LLC
    Inventors: Steven Sprouse, Satish B. Vasudeva, Rodney Brittner