Patents Examined by David X Yi
  • Patent number: 10228887
    Abstract: Provided are a computer program product, system, and method for considering input/output workload and space usage at a plurality of logical devices to select one of the logical devices to use to store an object. A determination is made of a logical device to store the object based on workload scores for each of the logical devices indicating a level of read and write access of objects in the logical device and space usage of the logical devices. The object is written to the determined logical device.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Anglin, Arthur John Colvig, Michael G. Sisco
  • Patent number: 10152272
    Abstract: A data mirroring control apparatus includes a command distributing unit configured to transmit a first write command to a plurality of mirroring storage devices, the first write command including an instruction for data requested by a host to be written; and a memory lock setting unit configured to set a memory lock on the data requested by the host to be written among data stored in a host memory and configured to release the memory lock on the data after the data with the memory lock is written to the plurality of mirroring storage devices.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju-Pyung Lee
  • Patent number: 10141039
    Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 27, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • Patent number: 10133678
    Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 20, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yasuko Eckert, Syed Ali Jafri, Srilatha Manne, Gabriel Loh
  • Patent number: 10133503
    Abstract: Data blocks may be received and a hash value for a first data block of the data blocks may be determined. A location of a duplicate of the first data block being stored at a storage resource based on the hash value for the first data block may be determined. A first performance metric associated with retrieving a second stored data block that is proximate to the duplicate of the first data block stored at the storage resource may be determined and a second performance metric associated with retrieving a second hash value corresponding to the second stored data block may be determined. The second stored data block proximate to the duplicate of the first data block may be retrieved in response to the first performance metric not exceeding the second performance metric.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 20, 2018
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Ronald Karr, Ethan L. Miller
  • Patent number: 10114744
    Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kamyar Souri, Andrew J. Tomlin, Dmitry S. Obukhov, Jing Booth, Mei-Man L. Syu
  • Patent number: 10101937
    Abstract: A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A hashed storage area can enable a quick lookup of densely addressed information by using a portion of the key to determine a location of a node entry. A sorted storage area can enable compact storage of sparse information by storing node entries that currently exist and allowing the entries to be searched. By offering both types of storage in a node, a node can be optimized for both dense and sparse information. A node entry can include a link to a next node or the physical address for the storage request.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 16, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Patent number: 10097378
    Abstract: Various systems and methods for implementing efficient TCAM resource sharing are described herein. Entries are allocated across a plurality of ternary content addressable memories (TCAMs), with the plurality of TCAMs including a primary TCAM and a secondary TCAM, where the entries are allocated by sequentially accessing a plurality of groups of value-mask-result (VMR) entries, with each group having at least one VMR entry associated with the group, and iteratively analyzing the VMR entries associated with each group to determine a result set of VMR entries, with the result set being a subset of VMR entries from the plurality of groups of VMR entries, and the result set to be stored in the primary TCAM.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 9, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Xuanming Dong, Vijaya Kumar Kulkarni, Cesare Cantù
  • Patent number: 10095632
    Abstract: Disclosed aspects relate to memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA). An access relationship is monitored between a set of hardware memory components and a set of software assets. A set of memory affinity data is stored. The set of memory affinity data indicates the access relationship between the set of software assets and the set of hardware memory components. Using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets is determined. Based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components is executed.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mehulkumar Patel, Vaidyanathan Srinivasan, Venkatesh Sainath
  • Patent number: 10089017
    Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: October 2, 2018
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Yiren Huang, Yong Wang, Kui Lin
  • Patent number: 10083123
    Abstract: Examples provide a page-fault latency feedback metric to determine performance of workloads or virtual machines (VMs) running on a VM host in a cluster. A hypervisor induces page-faults by varying a memory limit associated with a VM. Page-fault latencies are measured at each of the varying memory limits. A performance loss occurring at each page-fault latency is measured and converted to a performance score. A page-fault translation table is constructed based on the page-fault latencies and assigned performance scores. When a page-fault occurs during execution of a workload on a VM host in the cluster, a cluster manager maps the page-fault latency associated with the page-fault to a performance score in the page-fault translation table. The cluster manager computes a current workload performance or VM performance based on the page-fault latency and the performance score.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 25, 2018
    Assignee: VMware, Inc.
    Inventors: Ishan Banerjee, Jui-Hao Chiang, Kiran Tati, Preeti Agarwal
  • Patent number: 10078548
    Abstract: According to one embodiment, a memory controller controlling write to and read from a 3D NAND flash memory including a plurality of blocks, one block being constituted by a plurality of pages stacked in a depth direction includes a frame generator that generates frame data including an error detecting code or an error correcting code, and a frame divider that divides the frame data to generate a plurality of divided frames including a first divided frame and a second divided frame. The first divided frame and the second divided frame are written into different pages from one another.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: September 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Haga
  • Patent number: 10078597
    Abstract: A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: September 18, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Viswanath Mohan
  • Patent number: 10055350
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for pre-fetching data. The methods, systems, and apparatus include actions of providing a request for data to an input-output device and receiving a set of memory addresses for the requested data. Additional actions include determining a subset of the memory addresses, providing a request for a processor to pre-fetch or inject data corresponding to the subset of the memory addresses, and receiving the requested data and the set of memory addresses. Additional actions include determining that the received data includes data for the subset of memory addresses that has been requested to be pre-fetched or injected, storing the data for the subset of memory addresses in a cache of the processor, and storing remaining data of the received data for the memory addresses in a main memory.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: August 21, 2018
    Assignee: Google LLC
    Inventors: Rama Krishna Govindaraju, Liqun Cheng, Parthasarathy Ranganathan
  • Patent number: 10048886
    Abstract: A method of providing a file system for an electronic device includes organizing a plurality of Non-Volatile Dual In-Line Memory Module-Ps (NVDIMM-Ps) of a memory device of the electronic device into a plurality of groups based on location information of the NVDIMM-Ps, and creating a single File System Instance (FSI) for each group included in the plurality of groups.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 14, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Vishak Guddekoppa
  • Patent number: 10037140
    Abstract: A method includes a processing module of a storage unit of a dispersed storage network (DSN) monitoring input/output (IO) rates of a plurality of disk drives, where access requests for encoded data slices occur at varying rates. The method continues with the processing module determining that the IO rate of a disk drive is exceeding a desired maximum IO rate and identifying a pending access request for an encoded data slice stored in the disk drive. The method continues with the processing module evaluating disk drive processing rates of other storage units that are storing other encoded data slices of a set of encoded data slices that includes the encoded data slice to determine whether the encoded data slice is needed to satisfy the pending access request. When the encoded data slice is needed, the method continues with the processing module migrating the encoded data slice to another disk drive.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Baptist, Joseph Martin Kaczmarek
  • Patent number: 10037159
    Abstract: A memory system includes a memory device including a plurality of blocks and a plurality of page buffers which respectively correspond to the blocks, wherein each of the blocks includes a plurality of pages in which data is stored, and a controller suitable for backing up data, which is stored in a memory included in the controller, in the page buffers when an operation mode is about to change to a power save mode.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 31, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Jae Shin, Jong-Ju Park, Young-Jin Park
  • Patent number: 10019168
    Abstract: In general, the technology relates to a method and system for writing data to persistent storage. More specifically, embodiments of the technology relate to writing data to vaulted memory segments in persistent storage using pre-defined multicast address groups. Further, embodiments of the technology take into account the current state of the persistent storage in order to select the vaulted memory segments in which to store the data.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 10, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael W. Shapiro, Mikhail Orel
  • Patent number: 10013171
    Abstract: A method for reducing stress on a RAID under rebuild is disclosed herein. In one embodiment, such a method includes performing the following actions while the RAID is undergoing a rebuild process: (1) redirect writes intended for the RAID to a temporary storage area located on a same primary storage system as the RAID, and (2) redirect reads intended for the RAID to a secondary storage system configured to store a copy of data in the RAID. The method is further configured to perform the following actions upon completing the rebuild process: (3) update the rebuilt RAID to reflect writes made to the temporary storage area during the rebuild process, and (4) redirect reads and writes to the rebuilt RAID. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Herve G. P. Andre, Rashmi Chandra, Glynis G. Dsouza, Larry Juarez, Tony Leung, Igor Popov, Jacob L. Sheppard, Todd C. Sorenson
  • Patent number: 10013356
    Abstract: The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor is generating the stream of data accesses, the system examines a sequence of strides associated with the stream of data accesses. Next, upon detecting a pattern having a single constant stride in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the single constant stride. Similarly, upon detecting a recurring pattern having two or more different strides in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the recurring pattern having two or more different strides.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 3, 2018
    Assignee: ORACLE INTERNAIONAL CORPORATION
    Inventor: Yuan C. Chou